Abstract: An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.

Abstract: This application provides a chip package structure. The chip package structure includes: a substrate and a chip, and further includes: a heat dissipation ring fastened onto the substrate and a planar heat pipe radiator covering the heat dissipation ring. The substrate, the heat dissipation ring, and the planar heat pipe radiator form a space to enclose the chip. A first metal thin film is disposed on a surface, facing the chip, of the planar heat pipe radiator, and the chip is thermally coupled to the first metal thin film by using a sintered metal layer.

Abstract: A packaged chip, including a package structure, a redistribution structure, and a carrier, where the package structure includes a first chip and a second chip adjacent to the first chip. The redistribution structure is configured to electrically connect the first chip and the carrier, and is configured to electrically connect the second chip and the carrier. The redistribution structure includes a main body made of an insulating material and a bump solder array welded to a lower surface of the main body. A metal redistribution wire group and a metal interconnection wire group that has a curve or bend design are disposed in the main body. An upper surface of the main body of the redistribution structure adheres to a lower surface of the first chip and a lower surface of the second chip. The redistribution structure is welded to an upper surface of the carrier.

Abstract: The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier. The redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure.

Abstract: The present disclosure discloses a semiconductor apparatus and method of manufacturing. The apparatus includes: a circuit device and a heat sink fin that are disposed in a laminated manner, and a thermal interface material layer located between the circuit device and the heat sink fin. A packaging layer is disposed around a side wall of the circuit device. A first surface of the thermal interface material layer is thermally coupled to the circuit device and the packaging layer, and a second surface is thermally coupled to the heat sink fin. In the foregoing solution, the packaging layer and the circuit device are both thermally coupled to the thermal interface material layer, a contact area between the circuit device and the thermal interface material layer is increased.

Abstract: A packaged chip, including a package structure, a redistribution structure, and a carrier, where the package structure includes a first chip and a second chip adjacent to the first chip. The redistribution structure is configured to electrically connect the first chip and the carrier, and is configured to electrically connect the second chip and the carrier. The redistribution structure includes a main body made of an insulating material and a bump solder array welded to a lower surface of the main body. A metal redistribution wire group and a metal interconnection wire group that has a curve or bend design are disposed in the main body. An upper surface of the main body of the redistribution structure adheres to a lower surface of the first chip and a lower surface of the second chip. The redistribution structure is welded to an upper surface of the carrier.

Abstract: An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.

Abstract: The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier. The redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure.

Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: The subject invention relates to a semiconductor package and method of manufacturing the same. The semiconductor package of the subject invention comprises a substrate with a through hole penetrating therethrough; a semiconductor chip positioned on the substrate covering the through hole; and a thermal conductive device filling the through hole and contacting the semiconductor chip. According to the subject invention, the thermal resistance in the structure of the semiconductor package is substantially reduced and thus desirable performance of heat spreading or dissipation is achieved. In addition, the production cost and size of the semiconductor package are also reduced.

Abstract: The subject invention relates to a semiconductor package and method of manufacturing the same. The semiconductor package of the subject invention comprises a substrate with a through hole penetrating therethrough; a semiconductor chip positioned on the substrate covering the through hole; and a thermal conductive device filling the through hole and contacting the semiconductor chip. According to the subject invention, the thermal resistance in the structure of the semiconductor package is substantially reduced and thus desirable performance of heat spreading or dissipation is achieved. In addition, the production cost and size of the semiconductor package are also reduced.

Abstract: The subject matter disclosed herein relates to methods to reduce warpage of a substrate.

Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

Abstract: The subject matter disclosed herein relates to methods to reduce warpage of a substrate.