Abstract: A method of fabricating final spacers having a target width comprises the following steps. Initial spacers, each having an initial width that is less than the target width, are formed over the opposing side walls of a gate electrode portion. The difference between the initial spacer width and the target width is determined. A second spacer layer having a thickness equal to the determined difference between the initial width of the initial spacers and the target width is formed upon the initial spacers and the structure. The second spacer layer is etched to leave second spacer layer portions extending from the initial spacers to form the final spacers.

Abstract: An improved method of patterning resist protective dielectric layer and preferably protective silicon dioxide layer is described. The method consists of two sequential etching steps, the first one being a timed plasma etching process and the second one being a timed wet etching process. Plasma etching is used to remove approximately 70%-90% of the RPO film thickness and wet etching is used to remove the remaining 10%-30% of the film thickness. The two-step etching process achieves superior dimensional control, a non-undercut profile under the resist mask and prevents resist mask peeling from failure of adhesion at the mask/RPO film interface. The improved method has wide applications wherever and whenever RPO film is used in the process flow for fabricating semiconductor devices.

Abstract: A method for plasma etching a semiconductor feature to improve an etching profile including providing a semiconductor wafer comprising a first feature opening anisotropically etched though a thickness portion of at least one dielectric insulating layer; anisotropically etching a second feature opening overlying and at least partially encompassing the first feature opening according to a reactive ion etch (RIE) process to leave an unetched portion surrounding a first feature opening portion at about a bottom portion level of the second feature opening; and, plasma treating the first and second openings with a plasma formed of a mixture of oxygen and nitrogen plasma source gases including an applying an independently variable RF bias power source to the semiconductor wafer to remove the unetched portion.

Abstract: An undesirable side effect of some processes that are used for forming dual gate devices is the formation of defects at the interface between the two oxide layers of different thickness. This problem has been solved by preceding the HF wet dip (that is used to thin out a selected area of oxide) with exposure of the photoresist to a low power plasma that includes some oxygen. This treatment removes unsaturated chemical bonds from the resist surface and prevents the formation of SiC based defects. Such defects could cause polysilicon lines to short or open, depending on their size.