Patents by Inventor Jyh-Shyang Jenq
Jyh-Shyang Jenq has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948975Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.Type: GrantFiled: October 24, 2021Date of Patent: April 2, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
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Patent number: 11387148Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.Type: GrantFiled: May 12, 2020Date of Patent: July 12, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
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Publication number: 20220045170Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.Type: ApplicationFiled: October 24, 2021Publication date: February 10, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
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Patent number: 11189695Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.Type: GrantFiled: December 4, 2019Date of Patent: November 30, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
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Patent number: 10978398Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.Type: GrantFiled: January 1, 2020Date of Patent: April 13, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
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Publication number: 20200273758Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.Type: ApplicationFiled: May 12, 2020Publication date: August 27, 2020Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
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Patent number: 10692777Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.Type: GrantFiled: August 2, 2018Date of Patent: June 23, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
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Patent number: 10643997Abstract: A semiconductor device includes at least a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.Type: GrantFiled: July 17, 2017Date of Patent: May 5, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Tong-Jyun Huang, Shih-Hung Tsai, Jia-Rong Wu, Tien-Chen Chan, Yu-Shu Lin, Jyh-Shyang Jenq
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Publication number: 20200135647Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.Type: ApplicationFiled: January 1, 2020Publication date: April 30, 2020Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
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Publication number: 20200111871Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.Type: ApplicationFiled: December 4, 2019Publication date: April 9, 2020Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
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Patent number: 10566285Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.Type: GrantFiled: June 2, 2016Date of Patent: February 18, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
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Patent number: 10546922Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.Type: GrantFiled: February 6, 2018Date of Patent: January 28, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang
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Patent number: 10541304Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a spacer adjacent to the gate structure; forming a recess adjacent to the spacer; forming a buffer layer in the recess, wherein the buffer layer comprises a crescent moon shape; and forming an epitaxial layer on the buffer layer.Type: GrantFiled: May 17, 2018Date of Patent: January 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
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Patent number: 10497810Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first spacer adjacent to the first fin-shaped structure and a second spacer adjacent to the second fin-shaped structure; and using the first spacer and the second spacer as mask to remove part of the substrate for forming a third fin-shaped structure on the first region and a fourth fin-shaped structure on the second region, in which the third fin-shaped structure includes a first top portion and a first bottom portion and the fourth fin-shaped structure includes a second top portion and a second bottom portion.Type: GrantFiled: January 21, 2019Date of Patent: December 3, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Chih-Kai Hsu, Yu-Hsiang Hung, Jyh-Shyang Jenq
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Publication number: 20190157445Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first spacer adjacent to the first fin-shaped structure and a second spacer adjacent to the second fin-shaped structure; and using the first spacer and the second spacer as mask to remove part of the substrate for forming a third fin-shaped structure on the first region and a fourth fin-shaped structure on the second region, in which the third fin-shaped structure includes a first top portion and a first bottom portion and the fourth fin-shaped structure includes a second top portion and a second bottom portion;Type: ApplicationFiled: January 21, 2019Publication date: May 23, 2019Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Chih-Kai Hsu, Yu-Hsiang Hung, Jyh-Shyang Jenq
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Patent number: 10263095Abstract: A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed between the two sub regions. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed on the semiconductor layer in the sub regions and on the substrate in the dummy region. The substrate and the semiconductor layer are removed by using the patterned mask layer as a mask, thereby forming a plurality of fin structures in the sub regions and a plurality of dummy fin structures in the dummy region.Type: GrantFiled: May 31, 2018Date of Patent: April 16, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Chih-Kai Hsu, Jyh-Shyang Jenq
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Patent number: 10256146Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.Type: GrantFiled: January 14, 2018Date of Patent: April 9, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chao-Hung Lin, Chih-Kai Hsu, Jyh-Shyang Jenq
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Patent number: 10236383Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, wherein the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.Type: GrantFiled: March 8, 2018Date of Patent: March 19, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Chih-Kai Hsu, Yu-Hsiang Hung, Jyh-Shyang Jenq
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Publication number: 20180342426Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.Type: ApplicationFiled: August 2, 2018Publication date: November 29, 2018Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
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Patent number: 10141432Abstract: A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.Type: GrantFiled: September 5, 2017Date of Patent: November 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq