Abstract: This invention relates to a method for forming a dielectric layer, more particularly, to a method for forming a silicate dielectric layer. The first step of the present invention is to form a silicate layer on the substrate of the wafer by using a physical vapor deposition (PVD) procedure. The silicate layer is a hafnium silicate (HfSi) layer or a zirconium silicate (ZrSi) layer. Then the silicate layer is treated to become a gate dielectric layer or an inter-layer dielectric layer which has higher a dielectric constant by using a rapid thermal annealing (RTA) procedure in a environment which is filled of nitrogen or ammonia.

Abstract: A method for forming an oxidation-resistant structure for a MIM (metal-insulator-metal) capacitor is disclosed. The method is provided an oxidation-resistant barrier layer such as TaN is deposited by reactive sputtering method in the node-contact hole opening within a first ILD (inter layer dielectric) layer on the substrate. The method is also provided a first electrode plate (bottom electrode) such as Ta—Ru—N layer that has good oxygen diffusion barrier, good thermal stability, and low resistivity, is deposited on the storage-node (SN) hole opening. Further, the dielectric layer with high dielectric constant is between the first electrode and second electrode (upper electrode) to increase the capacitance of the MIM capacitor.

Abstract: In the present invention, a method of forming multitude of growth rates of oxide layer on the surface of a substrate is provided. The method comprises providing a first oxide layer on the substrate. A photoresist layer is formed on the first oxide layer. The photoresist layer exposes a portion of the first oxide layer. The exposed portion of the first oxide layer is subjected to plasma fluoridation. Then the photoresist layer is removed. Again, the first oxide layer is removed and a second oxide layer is formed on the substrate.

Abstract: A method for forming an integrated circuit device that incorporate both an array of memory cells and an array of logic circuits on a single chip or substrate is disclosed. The substrate has a transfer field effect transistor (FET) with a first gate electrode and a first source/drain region formed in and on a embedded DRAM region of the substrate and has a logic FET with a second gate electrode and a second source/drain region formed in and on a logic circuit region of the substrate. Next, a dielectric layer was deposited over the exposing surface of said transfer FET and above of the logic FET. Moreover, the dielectric layer was polished until upper surface of the first gate electrode and the second gate electrode is exposed. Subsequently, a photoresist layer is formed over the dielectric layer and the first gate electrode. And then the dielectric layer was etched until upper surface of the logic FET is exposed. Next, the photoresist layer was removed.

Abstract: A method is desired for making an array of dynamic random access memory (DRAM) cells having stacked capacitors with increased capacitance. The method involves forming a bottom electrode having a lower and upper fin-shaped portion in which a vertical extension is formed on the lower fin-shape portion at the same time that the upper fin is formed. This increases the capacitance of the stacked capacitor. The bottom electrode is formed by patterning a thick expendable silicon oxide layer and an underlying doped polysilicon layer (lower fin portion). Another polysilicon layer (upper fin portion is conformally coated over the thick insulating layer and patterned with an etch mask, which is smaller than the patterned insulating layer. An anisotropic etch is performed that forms the upper fin portion, the vertical extension on the lower fin portion and electrically isolates the array of electrodes.