Abstract: A power controller is provided. The power controller has a peak current setting unit utilized for deciding a peak current value according to a divided input voltage and a current limit turn-on time value. The comparator sends a first trigger signal once a current value of a power switch of the power system reaches the peak current value. The turn-on time calculation module defines the number of current limit operations by using the count of first trigger signals received in a calculation time period and then processes a recursive calculation to calculate a turn-on time value according to the current limit turn-on time value, the number of current limit operations, and a target number of current limit operations. The timer transmits a second trigger signal when the set turn-on time value is counted. The switch control module turns off the power switch when receiving one of the first and the second trigger signal.

Abstract: A power controller is provided. The power controller has a peak current setting unit utilized for deciding a peak current value according to a divided input voltage and a current limit turn-on time value. The comparator sends a first trigger signal once a current value of a power switch of the power system reaches the peak current value. The turn-on time calculation module defines the number of current limit operations by using the count of first trigger signals received in a calculation time period and then processes a recursive calculation to calculate a turn-on time value according to the current limit turn-on time value, the number of current limit operations, and a target number of current limit operations. The timer transmits a second trigger signal when the set turn-on time value is counted. The switch control module turns off the power switch when receiving one of the first and the second trigger signal.

Abstract: A converter control system includes an analog-to-digital converter, a filter and a control module. The analog-to-digital converter digitalizes a different-time and a real-time feedback voltage. The filter bases on the different-time feedback voltage to sample a historical average feedback voltage. The control module receives the real-time feedback voltage, bases on the historical average feedback voltage to detect a load status of the converter, and bases on the real-time feedback voltage and the historical average feedback voltage to derive a voltage difference. The control module applies a control duty cycle to control the load switch. While the control module detects that the load status switches to a heavy-load status and the voltage difference reaches the threshold voltage, the control duty cycle is increased. While the control module detects that the load status switches to the light-load status and the voltage difference reaches the threshold voltage, the control duty cycle is decreased.

Abstract: A power control system is electrically connected to a power function circuit including a power circuit, a coil module, a switch, and a load circuit, and includes at least one timer, a zero-current trigger unit, a status control unit, and a driver unit. The status control unit has a first status interval, a second status interval, a third status interval and a fourth status. The power control method triggers the status control unit to change the status interval when a counting time reaches one specific time interval corresponding one status interval. When a coil voltage of the coil module drops to zero from a voltage larger than a positive threshold voltage in the third status interval or the fourth status interval, the status control unit triggers to change the status interval, re-enters the first status interval, resets the timer, and triggers the driver unit to open the switch.

Abstract: A power control system is electrically connected to a power function circuit including a power circuit, a coil module, a switch, and a load circuit, and includes at least one timer, a zero-current trigger unit, a status control unit, and a driver unit. The status control unit has a first status interval, a second status interval, a third status interval and a fourth status. The power control method triggers the status control unit to change the status interval when a counting time reaches one specific time interval corresponding one status interval. When a coil voltage of the coil module drops to zero from a voltage larger than a positive threshold voltage in the third status interval or the fourth status interval, the status control unit triggers to change the status interval, re-enters the first status interval, resets the timer, and triggers the driver unit to open the switch.

Abstract: A converter control system includes an analog-to-digital converter, a filter and a control module. The analog-to-digital converter digitalizes a different-time and a real-time feedback voltage. The filter bases on the different-time feedback voltage to sample a historical average feedback voltage. The control module receives the real-time feedback voltage, bases on the historical average feedback voltage to detect a load status of the converter, and bases on the real-time feedback voltage and the historical average feedback voltage to derive a voltage difference. The control module applies a control duty cycle to control the load switch. While the control module detects that the load status switches to a heavy-load status and the voltage difference reaches the threshold voltage, the control duty cycle is increased. While the control module detects that the load status switches to the light-load status and the voltage difference reaches the threshold voltage, the control duty cycle is decreased.

Abstract: An integrated and simplified source driver system includes a scan driver and a data driver. The data driver has a signal controller and a plurality of data driver units each of which has a converter. The converter can convert a first control signal into display data, a driver-unit control signal and a second control signal. The data driver unit can correspondingly send a data drive signal to one of thin film transistors according to the display data and the driver-unit control signal. The second control signal is sent to the scan driver for generating a scan drive signal which is correspondingly sent to one of the thin film transistors. In a preferred embodiment, the first control signal includes an integrated drive-unit control command.

Abstract: A source driver system includes a scan driver and a data driver. The data driver has a signal controller, a data bus, a connector and a plurality of data driver units. The signal controller is connected with the connector with via the data bus to form a first connection relationship such that the data bus is capable of transmitting control signals from the signal controller to the connector. The connector connects with the data driver units via the data bus to form a second connection relationship such that the data bus is capable of transmitting the control signals from the connector to the corresponding data driver units. In a preferred embodiment, the data bus is further arranged to form a third connection relationship among the data driver units such that the data bus is capable of communicating a serial connection signal among the data driver units.

Abstract: A packet detector for a multi-band orthogonal frequency division multiplexing system includes a plurality of packet detection units each corresponding to a time frequency code for detecting packets according to a spreading sequence of the time frequency code, a comparison unit for comparing correlation values provided by division units of the plurality of packet detection units, and a packet decision module for determining a time frequency code and size of a fast Fourier transform sampling window according to output signals of the comparison unit, allowing a frequency band to be selected and synchronization to be executed.

Abstract: A phase locked loop (PLL), including a phase-frequency detector receiving two clock signals and outputting a phase detection signal corresponding to the phase difference between the two clock signals is provided. A controller receives the phase detection signal and generates a first control signal and a second control signal according to the phase detection signal, an oscillator receiving the first control signal and outputting a first output clock signal with a folded period corresponding to the first control signal and a loop divider receiving the second control signal and the first output clock signal dividing the frequency of the first output clock signal by an integer unfolding divisor corresponding to the second control signal and outputting a second output clock signal coupled to the phase-frequency detector. The PLL eliminates unlocked frequencies for all process imperfections, has decreased circuit area and provides a broad output bandwidth.

Abstract: A phase locked loop (PLL), including a phase-frequency detector receiving two clock signals and outputting a phase detection signal corresponding to the phase difference between the two clock signals is provided. A controller receives the phase detection signal and generates a first control signal and a second control signal according to the phase detection signal, an oscillator receiving the first control signal and outputting a first output clock signal with a folded period corresponding to the first control signal and a loop divider receiving the second control signal and the first output clock signal dividing the frequency of the first output clock signal by an integer unfolding divisor corresponding to the second control signal and outputting a second output clock signal coupled to the phase-frequency detector. The PLL eliminates unlocked frequencies for all process imperfections, has decreased circuit area and provides a broad output bandwidth.

Abstract: A pipelined adaptive decision feedback equalizer (DFE). The pipelined ADFE comprises a pre-processing unit, an adder, a feedback filter (FBF), a slicer, a delay unit, a weight-update block and a mapping circuit. The pre-processing unit comprising a plurality of PP coefficients filters a signal received from a channel, and outputs a PP output signal to the adder. The slicer outputs a decision signal based on an added signal output from the adder. The FBF comprising a plurality of FBF coefficients receives the decision signal and generates a FBF output signal to the delay unit. The delay unit outputs a delayed signal to the adder. The weight-update block adapts the FBF coefficients to cancel the post-cursor ISI and selects a plurality of coefficients from the FBF coefficients. The mapping circuit translates the FFF coefficients by a predetermined method to generate the PP coefficients output to the pre-processing unit.

Abstract: An apparatus and a method for compensating signal attenuation based on an equalizer. The apparatus Includes an auto gain controller, an analog-to-digital converter and an auto-gain-control mapping circuit. The auto gain controller is used for receiving an incoming analog signal and amplifying the received analog signal. The analog-to-digital convertor is used for converting the output of the auto gain controller into a digital signal. The output of the auto-gain-control mapping circuit is used to control the gain of the auto gain controller. The equalizer is connected to the output of the analog-to-digital converter to eliminate signal attenuation in the digital output of the analog-to-digital converter. The output of the auto-gain-control mapping circuit controls the gain of the auto gain controller based on the primary weight of the equalizer.

Abstract: The invention relates to an Overlap and Add circuit, and in particular, an adaptive Overlap and Add circuit. The adaptive OLA circuit comprises a detection unit, an estimator, and an OLA circuit. The detection unit estimates a channel property according to an OFDM signal received through a channel. The estimator estimates an OLA length in a current OFDM symbol of an OFDM signal according to a channel property. The OLA circuit copies an OLA signal to an FFT window in the current symbol according to the OLA length.

Abstract: A transceiver for echo and near-end crosstalk cancellation without a loop timing configuration. The transceiver comprises a receiver, a timing recovery circuit, a same-channel phase interpolator, an echo canceller, a near-channel phase interpolator and a near-end crosstalk (NEXT) canceller. The same-channel phase interpolator and the near-channel phase interpolator receive a phase choosing signal from the timing recovery circuit to determine a specific phase from different phases. The same-channel phase interpolator generates a same-channel phase-modified signal with the specific phase and outputs the phase-modified signal to the echo canceller to cancel an echo in the received signal. The near-channel phase interpolator generates a near-channel phase-modified signal with the specific phase and outputs the near-channel phase-modified signal to the NEXT canceller to cancel a NEXT signal in the received signal.

Abstract: A packet detector for a multi-band orthogonal frequency division multiplexing system includes a plurality of packet detection units each corresponding to a time frequency code for detecting packets according to a spreading sequence of the time frequency code, a comparison unit for comparing correlation values provided by division units of the plurality of packet detection units, and a packet decision module for determining a time frequency code and size of a fast Fourier transform sampling window according to output signals of the comparison unit, allowing a frequency band to be selected and synchronization to be executed.

Abstract: The present invention provides a packet detection device including a reception end for receiving signals; a matched filter coupled to the reception; a power meter coupled to the reception end and the matched filter for calculating power of signals received by the reception end; and a logic unit coupled to the matched filter and the power meter for determining whether a packet is received according to the values of the matched filter and power meter. The present invention is capable of de-spreading coefficients of a preamble sequence into first de-spread signals and second de-spread signals and determining a matched value such that the complexity and surface area of the hardware can be reduced so that the efficiency of detecting packets can be increased.

Abstract: An apparatus and a method for compensating signal attenuation based on an equalizer. The apparatus includes an auto gain controller, an analog-to-digital converter and an auto-gain-control mapping circuit. The analog-to-digital converter is used for receiving an incoming analog signal and amplifying the received analog signal. The analog-to-digital converter is used for converting the output of the auto gain controller into a digital signal. The output of the auto-gain-control mapping circuit is used to control the gain of the auto gain controller. The equalizer is connected to the output of the analog-to-digital converter to eliminate signal attenuation in the digital output of the analog-to-digital converter. The output of the auto-gain-control mapping circuit controls the gain of the auto gain controller based on the primary weight of the equalizer.

Abstract: A method of adjusting the weights of a blind equalizer. In the blind equalizer, an error signal e(n) is reset to zero as soon as the error signal e(n) reaches a predetermined value such as a maximum error signal value so that the weight vector W(n+1) is unaffected by the error signal e(n). Furthermore, the error signal e(n) is also reset to zero as soon as a second slicer output r2(n) changes from the original value due to an adjustment or transmission error and results in an inaccuracy of error signal e(n) so that the weight vector W(n+1) is unaffected by the error signal e(n).

Abstract: A pipelined adaptive decision feedback equalizer (DFE). The pipelined ADFE comprises a pre-processing unit, an adder, a feedback filter (FBF), a slicer, a delay unit, a weight-update block and a mapping circuit. The pre-processing unit comprising a plurality of PP coefficients filters a signal received from a channel, and outputs a PP output signal to the adder. The slicer outputs a decision signal based on an added signal output from the adder. The FBF comprising a plurality of FBF coefficients receives the decision signal and generates a FBF output signal to the delay unit. The delay unit outputs a delayed signal to the adder. The weight-update block adapts the FBF coefficients to cancel the post-cursor ISI and selects a plurality of coefficients from the FBF coefficients. The mapping circuit translates the FFF coefficients by a predetermined method to generate the PP coefficients output to the pre-processing unit.