Patents by Inventor JYH-WEEI HSIA

JYH-WEEI HSIA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9734271
    Abstract: In some embodiments, in a method for a semiconductor device having an interconnect structure, a design layout is received. A metal line in the design layout is identified, which has at least one via thereon and does not couple downward with an oxide diffusion region. The area of a gate oxide coupled with the metal line is obtained from the design layout. The method comprises determining whether the area of the gate oxide is greater than a first predetermined value. When the area of the gate oxide is greater than the first predetermined value, a charge release path is coupled with the metal line.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: August 15, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu Ching Lee, Jian-Hong Lin, Te-Liang Lee, Jyh-Weei Hsia
  • Publication number: 20170169152
    Abstract: In some embodiments, in a method for a semiconductor device having an interconnect structure, a design layout is received. A metal line in the design layout is identified, which has at least one via thereon and does not couple downward with an oxide diffusion region. The area of a gate oxide coupled with the metal line is obtained from the design layout. The method comprises determining whether the area of the gate oxide is greater than a first predetermined value. When the area of the gate oxide is greater than the first predetermined value, a charge release path is coupled with the metal line.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 15, 2017
    Inventors: YU CHING LEE, JIAN-HONG LIN, TE-LIANG LEE, JYH-WEEI HSIA