Patents by Inventor Jyoji Maeda

Jyoji Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4901351
    Abstract: A transmitter encoder has a gain selector for compressing the level of a horizontal sync signal component of a video intermediate frequency (IF) signal to scramble it, and an AM modulation degree controller for superposing a control signal, which indicates the timing for the level compression, on an FM audio IF signal in the form of AM modulation. The transmitter encoder further has an oscillator circuit for generating a sine wave with a horizontal frequency (fH) and an nfH sine wave having a frequency n times the horizontal frequency, and a mixer for mixing these sine waves to thereby provide the above control signal. A receiver decoder has an AM detector for detecting an AM component of the FM audio IF signal from the transmitter encoder to reproduce a composite signal and band filters for respectively extracting the fH and nfH sine waves from the reproduced composite signal.
    Type: Grant
    Filed: September 7, 1988
    Date of Patent: February 13, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Tanaka, Wataru Kuroiwa, Akinori Masuko, Jyoji Maeda, Shouji Uehara, Tsutomu Uekusa
  • Patent number: 4724337
    Abstract: An automatic gain control (AGC) detection circuit. The AGC detection circuit includes; a current source, first to fourth transistors whose emitters are connected in common to the current source, a reference voltage source for supplying the bases of the first and the second transistors with a reference voltage, input terminal means connected to the bases of the third and the fourth transistors for receiving an input signal, a power supply source for supplying the first to fourth transistors with a power supply voltage, first collector load means connected between the power supply source and a node connecting the collectors of the first and second transistors in common, second collector load means connected between the power supply source and another node connecting the collectors of the third and fourth transistors in common, and an output terminal means connected between the nodes for taking out an automatic gain control detection output.
    Type: Grant
    Filed: March 27, 1986
    Date of Patent: February 9, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jyoji Maeda, Kazuo Hasegawa, Yasunori Miyahara