Patents by Inventor Jyonu Ri

Jyonu Ri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7485923
    Abstract: A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: February 3, 2009
    Assignee: NEC Corporation
    Inventors: Hisashi Takemura, Risho Koh, Yukishige Saito, Jyonu Ri
  • Patent number: 7211517
    Abstract: A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: May 1, 2007
    Assignee: NEC Corporation
    Inventors: Yukishige Saito, Risho Koh, Jyonu Ri, Hisashi Takemura
  • Publication number: 20050151172
    Abstract: A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.
    Type: Application
    Filed: October 2, 2002
    Publication date: July 14, 2005
    Inventors: Hisashi Takemura, Risho Koh, Yukishige Saito, Jyonu Ri
  • Publication number: 20040209438
    Abstract: A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.
    Type: Application
    Filed: May 11, 2004
    Publication date: October 21, 2004
    Inventors: Yukishige Saito, Risho Koh, Jyonu Ri, Hisashi Takemura