Patents by Inventor Jyoti Arya

Jyoti Arya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CORRECTING FOR OFFSET-ERRORS IN A PLL/DLL
    Publication number: 20140145768
    Abstract: The main feedback loop of a PLL/DLL receives a reference clock and an output clock as inputs, and operates to achieve one or both of a phase and a frequency lock of the output clock with respect to the reference clock. The PLL/DLL includes an RS-latch connected to receive the output clock and the reference clock. The RS-Latch generates a digital output representing a phase difference between the reference clock and the output clock. A correction block in the PLL/DLL receives the digital output and adjusts an electrical characteristic of the main feedback loop by a value that is based on a polarity of the digital output. Effects of offset-errors in the PLL/DLL are thereby minimized or corrected for.
    Type: Application
    Filed: February 8, 2013
    Publication date: May 29, 2014
    Applicant: COSMIC CIRCUITS PVT LTD
    Inventors: Rishi Mathur, Jyoti Arya, Prasenjit Bhowmik
  • Correcting for offset-errors in a PLL/DLL
    Patent number: 8723566
    Abstract: The main feedback loop of a PLL/DLL receives a reference clock and an output clock as inputs, and operates to achieve one or both of a phase and a frequency lock of the output clock with respect to the reference clock. The PLL/DLL includes an RS-latch connected to receive the output clock and the reference clock. The RS-Latch generates a digital output representing a phase difference between the reference clock and the output clock. A correction block in the PLL/DLL receives the digital output and adjusts an electrical characteristic of the main feedback loop by a value that is based on a polarity of the digital output. Effects of offset-errors in the PLL/DLL are thereby minimized or corrected for.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: May 13, 2014
    Assignee: Cadence AMS Design India Private Limited
    Inventors: Rishi Mathur, Jyoti Arya, Prasenjit Bhowmik