Patents by Inventor Jyoti Kiron Bhardwaj
Jyoti Kiron Bhardwaj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7491649Abstract: A plasma processing apparatus includes a chamber having a support for a substrate, and at least one gas inlet into the chamber. The apparatus is configured to alternately introduce an etch gas and a deposition gas into the chamber through the at least on gas inlet, and to strike a plasma into the etch gas and the deposition gas alternately introduced into the chamber. The apparatus is further equipped with an attenuation device for reducing and/or homogenizing the ion flux from the plasma substantially without affecting the neutral radical number density.Type: GrantFiled: March 16, 2005Date of Patent: February 17, 2009Assignee: Surface Technology Systems PLCInventors: Jyoti Kiron Bhardwaj, Leslie Michael Lea
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Patent number: 7306745Abstract: A workpiece is processed in a chamber by striking a plasma in the chamber, treating the workpiece by cyclically adjusting the processing parameters between at least a first step having a first set of processing parameters and a second step having a second set of process parameters, wherein the plasma is stabilized during the transition between the first and second steps. These steps may comprise cyclic etch and deposition steps. One possibility for stabilizing the plasma is by matching the impedance of the plasma to the impedance of the power supply which provides energy to the plasma, by means of a matching unit which can be controlled in a variety of ways depending upon the step type or time during the step. Another possibility is to prevent or reduce substantially variation in the pressure in the chamber between the first and second steps.Type: GrantFiled: April 12, 2000Date of Patent: December 11, 2007Assignee: Surface Technology Systems PLCInventors: Jyoti Kiron Bhardwaj, Leslie Michael Lea, Edward Guibarra
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Patent number: 7141504Abstract: There is disclosed a method of treating a substrate material or a film present on the material surface comprising cyclically performing the following steps: (a) etching the material or film; (b) depositing or forming a passivation layer on the surfaces of an etched feature; and (c) selectively removing the passivation layer from the etched feature in order that the etching proceeds in a direction substantially perpendicular to the material or film surface. At least one of the steps (a) or (b) is performed in the absence of a plasma. Also disclosed is an apparatus for performing the method.Type: GrantFiled: July 23, 1999Date of Patent: November 28, 2006Assignee: Surface Technology Systems PLCInventor: Jyoti Kiron Bhardwaj
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Patent number: 6947653Abstract: A planar lightwave circuit includes at least one optical waveguide core, and at least one feature proximate the core having a stress-engineered property to balance stress and therefore minimize birefringence affecting the core. A protective passivation layer is formed over the core and the feature to be substantially non-interfering with the balanced stress provided by the feature. The stress balancing feature may be an overcladding layer formed over the core, doped to have a coefficient of thermal expansion approximately matched to that of an underlying substrate, to symmetrically distribute stress in an undercladding between the overcladding and the substrate, away from the core. The protective passivation layer is formed to have a coefficient of thermal expansion approximately matched to that of the overcladding. In one exemplary embodiment, the passivation layer is formed from silicon nitride. Related concepts of stress release grooves, and core overetching, are also disclosed.Type: GrantFiled: October 12, 2001Date of Patent: September 20, 2005Assignee: JDS Uniphase CorporationInventors: Jyoti Kiron Bhardwaj, Robert James Brainard, Zi-Wen Dong, David Dougherty, Erik W. Egan, Niranjan Gopinathan, David K. Nakamoto, Thomas Thuan Nguyen, Sanjay M. Thekdi, Anantharaman Vaidyanathan, Hiroaki Yamada, Yingchao Yan
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Patent number: 6929784Abstract: A ClF3 gas generation system is provided with supply sources of chlorine (3) (for example a cylinder of compressed chlorine) and fluorine (4) (for example a fluorine generator) connected into a gas reaction chamber (2) enabling generation of ClF3 gas. The reaction chamber has a valved outlet (C) for the supply of the ClF3 gas to a process chamber for immediate local use.Type: GrantFiled: March 6, 2000Date of Patent: August 16, 2005Assignee: Surface Technology Systems plcInventors: Jyoti Kiron Bhardwaj, Nicholas Shepherd, Leslie Michael Lea, Graham Hodgson
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Patent number: 6926871Abstract: A gas generator system is provided wherein supply sources for halogenated gases, including pure molecular halogens, are connected into a gas reaction chamber, or chamber system, to enable generation of a predetermined gas for localized use in a subsequent process. The reaction chamber has a valved outlet for direct supply of the generated gas to a single or multiple chamber processing tool or process chamber. Thus it is possible, for example, to provide for the localized generation of reactive process gases.Type: GrantFiled: March 6, 2000Date of Patent: August 9, 2005Assignee: Surface Technology Systems plcInventor: Jyoti Kiron Bhardwaj
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Patent number: 6697553Abstract: A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).Type: GrantFiled: February 15, 2002Date of Patent: February 24, 2004Assignee: JDS Uniphase CorporationInventors: Jyoti Kiron Bhardwaj, Robert James Brainard, David J. Chapman, Douglas E. Crafts, Zi-Wen Dong, David Dougherty, Erik W. Egan, James F. Farrell, Mark B. Farrelly, Niranjan Gopinathan, Kenzo Ishida, David K. Nakamoto, Thomas Thuan Nguyen, Suresh Ramalingam, Steven M. Swain, Sanjay M. Thekdi, Anantharaman Vaidyanathan, Hiroaki Yamada, Yingchao Yan
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Publication number: 20030156789Abstract: A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).Type: ApplicationFiled: February 15, 2002Publication date: August 21, 2003Inventors: Jyoti Kiron Bhardwaj, Robert James Brainard, David J. Chapman, Douglas E. Crafts, Zi-Wen Dong, David Dougherty, Erik W. Egan, James F. Farrell, Mark B. Farrelly, Niranjan Gopinathan, Kenzo Ishida, David K. Nakamoto, Thomas Thuan Nguyen, Suresh Ramalingam, Steven M. Swain, Sanjay M. Thekdi, Anantharaman Vaidyanathan, Hiroaki Yamada, Yingchao Yan
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Patent number: 6602433Abstract: A substrate is treated by supplying an etchant and/or deposition gas into a chamber in which the substrate is situated. In order to avoid the problems associated with transportation of toxic gases, the gases required for such processes are delivered directly from a gas generation and delivery system positioned locally to the chamber.Type: GrantFiled: December 18, 2000Date of Patent: August 5, 2003Assignee: Surface Technology Systems PLCInventors: Jyoti Kiron Bhardwaj, Nicholas Shepherd, Leslie Michael Lea
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Patent number: 6602384Abstract: A workpiece support includes a support body having a surface for supporting a workpiece thereon, and at least one Langmuir probe embedded within the support body. The Langmuir probe is covered by a layer of semiconductor or insulator. The workpiece support further includes a mechanism for intermittently feeding RF power to Langmuir probe, and for measuring a discharge of a capacitor in series with the Langmuir probe while the RF power is not supplied to the Langmuir probe.Type: GrantFiled: July 2, 2001Date of Patent: August 5, 2003Assignee: Surface Technology Systems, PLCInventors: Jyoti Kiron Bhardwaj, Leslie Michael Lea
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Publication number: 20030072548Abstract: A planar lightwave circuit includes at least one optical waveguide core, and at least one feature proximate the core having a stress-engineered property to balance stress and therefore minimize birefringence affecting the core. A protective passivation layer is formed over the core and the feature to be substantially non-interfering with the balanced stress provided by the feature. The stress balancing feature may be an overcladding layer formed over the core, doped to have a coefficient of thermal expansion approximately matched to that of an underlying substrate, to symmetrically distribute stress in an undercladding between the overcladding and the substrate, away from the core. The protective passivation layer is formed to have a coefficient of thermal expansion approximately matched to that of the overcladding. In one exemplary embodiment, the passivation layer is formed from silicon nitride. Related concepts of stress release grooves, and core overetching, are also disclosed.Type: ApplicationFiled: October 12, 2001Publication date: April 17, 2003Applicant: Scion Photonics, Inc.Inventors: Jyoti Kiron Bhardwaj, Robert James Brainard, Zi-Wen Dong, David Dougherty, Erik W. Egan, Niranjan Gopinathan, David K. Nakamoto, Thomas Thuan Nguyen, Sanjay M. Thekdi, Anantharaman Vaidyanathan, Hiroaki Yamada, Yingchao Yan
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Patent number: 6534922Abstract: A plasma processing apparatus includes a processing chamber having a working volume. A single Radio-Frequency (RF) plasma generating antenna is positioned outside the working volume for inducing an electric field in the working volume. A dielectric trough extends into a wall of the chamber. The antenna is non-planar and transfers power through at least one wall and the base of the trough.Type: GrantFiled: June 20, 2001Date of Patent: March 18, 2003Assignee: Surface Technology Systems, PLCInventors: Jyoti Kiron Bhardwaj, Leslie Michael Lea
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Publication number: 20020185226Abstract: A solenoidal magnetic field generated by a coil around the upper chamber A acts as a magnetic plasma attenuator. By judicious adjustment of the magnetic field strength, a dense plasma region forms inside the tube and adjacent to an antenna and is at least partially trapped by the field lines. These field lines intersect the wall of the upper chamber near or on the lid, and either on the upper chamber wall near its base, or on the lid or upper walls of the lower chamber. Significant numbers of radicals can be created in the upper chamber, which then diffuse into the lower chamber. The associated ion flux is reduced, however, because of losses where the field lines intersect the walls, thereby ensuring that the ratio of ion numbers to radical numbers reaching the wafer is reduced.Type: ApplicationFiled: January 14, 2002Publication date: December 12, 2002Inventors: Leslie Michael Lea, Janet Hopkins, Jyoti Kiron Bhardwaj, Huma Ashraf
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Patent number: 6458239Abstract: A plurality of antennae generate a plasma in the chamber containing a workpiece, and the relative outputs of the antennae are varied as a detector detects a property or parameter of the resultant plasma or process. The relative outputs of the antennae are controlled in accordance with the property or parameter detected. The detector, which detects the property or parameter at or near the workpiece location, is a Langmuir probe which is shielded from the plasma by a semiconductor or insulating layer and is driven.Type: GrantFiled: September 10, 1998Date of Patent: October 1, 2002Assignee: Surface Technology Systems plcInventors: Jyoti Kiron Bhardwaj, Leslie Michael Lea
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Publication number: 20020060523Abstract: A wafer processing chamber includes a wafer support, a dielectric window and coaxial coils located outside the dielectric window for inducing a plasma within the chamber. A variety of coil/dielectric windows are described together with protocols for their control.Type: ApplicationFiled: June 20, 2001Publication date: May 23, 2002Inventors: Jyoti Kiron Bhardwaj, Leslie Michael Lea
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Publication number: 20020025388Abstract: This invention relates to plasma processing apparatus and methods. Apparatus includes a chamber, a wafer support, antennae, a control module for controlling the antennae and responsive to associated detectors, which are located in or adjacent the wafer.Type: ApplicationFiled: July 2, 2001Publication date: February 28, 2002Inventors: Jyoti Kiron Bhardwaj, Leslie Michael Lea
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Patent number: 6261962Abstract: A sidewall passivation layer is deposited on an etched feature in a semiconductor substrate with a hydrocarbon deposition gas by introducing H2, determining certain mixture percentages for the hydrocarbon gas/H2 mix at which the etch rate for the substrate peaks, the etch rate begins to rise from a generally steady state, and/or the etch rate falls to zero, and then maintaining the mixture percentage within a selected range. Where the hydrocarbon gas/H2 mix is maintained at a percentage between the steady-state etch rate percentage and the peak etch rate percentage, then relatively high ion energies are used. Where the hydrocarbon gas/H2 mix is maintained at a percentage between the peak etch rate percentage and the percentage where the etch rate falls to zero, then relatively low ion energies are used.Type: GrantFiled: August 1, 1997Date of Patent: July 17, 2001Assignee: Surface Technology Systems LimitedInventors: Jyoti Kiron Bhardwaj, Huma Ashraf, Babak Khamsehpour, Janet Hopkins, Alan Michael Hynes, Martin Edward Ryan, David Mark Haynes
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Patent number: 6259209Abstract: A wafer processing chamber 11 includes a wafer support 12, a dielectyric window 13 and coaxial coils 15 and 16 located outside the dielectric window 13 for inducing a plasma within the chamber. A variety of coil/dielectric windows are described together with protocols for their control.Type: GrantFiled: September 26, 1997Date of Patent: July 10, 2001Assignee: Surface Technology Systems LimitedInventors: Jyoti Kiron Bhardwaj, Leslie Michael Lea
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Patent number: 6187685Abstract: There is disclosed a method and apparatus for etching a substrate. The method comprises the steps of etching a substrate or alternately etching and depositing a passivation layer. A bias frequency, which may be pulsed, may be applied to the substrate and may be at or below the ion plasma frequency.Type: GrantFiled: February 8, 1999Date of Patent: February 13, 2001Assignee: Surface Technology Systems LimitedInventors: Janet Hopkins, Ian Ronald Johnston, Jyoti Kiron Bhardwaj, Huma Ashraf, Alan Michael Hynes, Leslie Michael Lea
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Patent number: 6051503Abstract: This invention relates to methods for treatment of semiconductor substrates and in particular a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition, wherein one or more of the following parameters: gas flow rates, chamber pressure, plasma power, substrate bias, etch rate, deposition rate, cycle time and etching/deposition ratio vary with time.Type: GrantFiled: August 1, 1997Date of Patent: April 18, 2000Assignee: Surface Technology Systems LimitedInventors: Jyoti Kiron Bhardwaj, Huma Ashraf, Babak Khamsehpour, Janet Hopkins, Alan Michael Hynes, Martin Edward Ryan, David Mark Haynes