Patents by Inventor Jyotindra R. Shakya

Jyotindra R. Shakya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146320
    Abstract: Described herein is a mismatch shaping technique applied in digital-to-analog converters (DACs) for high pass filtering mismatch related errors. The mismatch shaping scheme is based on a zero mean error encoding technique, which can be applied directly to binary coded signals, without the use for binary to thermometer decoding and element shuffling. In at least one example, an apparatus is provided which comprises a mismatch shaping circuitry to receive an N-bit binary input bits and to generate an (N+1)-bit digital output. In at least one example, the apparatus further comprises a digital-to-analog converter to receive the (N+1)-bit digital output and to generate an analog output, wherein the mismatch shaping circuitry is to encode the (N+1)-bit digital output to shape mismatch errors in the digital-to-analog converter.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 2, 2024
    Applicant: Oregon State University
    Inventors: Jyotindra R. Shakya, Gabor C. Temes
  • Publication number: 20130321433
    Abstract: This disclosure provides systems, methods, and apparatus related to a the design of arrays of electrodes in a device which includes a light-guiding layer in optical contact with the electrodes. In one aspect, a device includes an array of electrodes, the electrodes include at least one edge having a non-linear shape. Specific design constraints may be placed on the shape of the non-linear edge of the electrodes.
    Type: Application
    Filed: September 6, 2012
    Publication date: December 5, 2013
    Applicant: QUALCOMM MEMS Technologies, Inc.
    Inventors: Ion Bita, Russel A. Martin, Marek Mienko, Jyotindra R. Shakya