Abstract: An anti-virus system for enforcing a virus monitoring and scanning process, the anti-virus and firewall system comprises a master CPU card, a plurality of slave CPU cards and a programmable logic. The master CPU card is used for controlling the virus monitoring and scanning process and dividing the virus monitoring and scanning process into a plurality of sub-processes. The plurality of slave CPU cards are controlled by the master CPU card in a software level and a hardware level, each of the plurality of slave CPU cards receives and processes one of the plurality of sub-processes then sends back to the master CPU card. The programmable logic controlled by the master CPU card for monitoring and controlling said plurality of slave CPU cards at a hardware level.

Abstract: A network interface system for transferring a data packet between a host system and a network includes multiple matchers and multiple queues. The matchers match the data packet with multiple rules from the host system to generate multiple matching results and allocate a transferring priority to the data packet according to the rules. The queues correspond to the matchers respectively. A queue of the queues stores information indicating the transferring priority for the data packet according to the matching results and priorities of matchers.

Abstract: A network interface system for transferring a data packet between a host system and a network includes multiple matchers and multiple queues. The matchers match the data packet with multiple rules from the host system to generate multiple matching results and allocate a transferring priority to the data packet according to the rules. The queues correspond to the matchers respectively. A queue of the queues stores information indicating the transferring priority for the data packet according to the matching results and priorities of matchers.

Abstract: A network interface system with packet filtering function is disclosed herein. The network interface system includes interfaces, a packet buffer and a controller. The packet buffer stores data packets received by the network interface system. The controller provides security defense for the host system and the network by filtering the data packets stored in the packet buffer. The controller controls the packet buffer abandoning a data packet if the data packet is identified as an unsafe packet. The controller also includes a regulator for controlling a transferring order of the data packets. Thus, the network interface system can drop unsafe data packet and transfer data packets considered as safe information. The data packets can be processed in a sequence according to preset priority rules.

Abstract: A computer-readable medium having computer-executable modules is disclosed. The computer-executable modules include a first session database for storing multiple sessions indicating information interchange between at least two communicating devices. The computer-executable modules further include a controller operable for selecting a session from the first session database according to a session update rate indicating the number of sessions updated in the first session database during a given period of time and for synchronizing the session from the first session database to a second session database.

Abstract: A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result, the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.

Abstract: The present disclosure provides an integrated VPN/Firewall system that uses both hardware (firmware) and software to optimize the efficiency of both VPN and firewall functions. The hardware portions of the VPN and firewall are designed in flexible and scalable layers to permit high-speed processing without sacrificing system security. The software portions are configured to provide interfacing with hardware components, report and rules management control.

Abstract: The present invention provides an integrated VPN/firewall system that uses bath hardware (firmware) and software to optimize the efficiency of both VPN and firewall functions. The hardware portions of the VPN and firewall are designed in flexible and scalable layers to permit high-speed processing without sacrificing system security. The software portions are adapted to provide interfacing with hardware components, report and rules management control.

Abstract: A network interface system with packet filtering function is disclosed herein. The network interface system includes interfaces, a packet buffer and a controller. The packet buffer stores data packets received by the network interface system. The controller provides security defense for the host system and the network by filtering the data packets stored in the packet buffer. The controller controls the packet buffer abandoning a data packet if the data packet is identified as an unsafe packet. The controller also includes a regulator for controlling a transferring order of the data packets. Thus, the network interface system can drop unsafe data packet and transfer data packets considered as safe information. The data packets can be processed in a sequence according to preset priority rules.

Abstract: A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result: the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.

Abstract: A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result, the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.

Abstract: An anti-virus system for enforcing a virus monitoring and scanning process, the anti-virus and firewall system comprises a master CPU card, a plurality of slave CPU cards and a programmable logic. The master CPU card is used for controlling the virus monitoring and scanning process and dividing the virus monitoring and scanning process into a plurality of sub-processes. The plurality of slave CPU cards are controlled by the master CPU card in a software level and a hardware level, each of the plurality of slave CPU cards receives and processes one of the plurality of sub-processes then sends back to the master CPU card. The programmable logic controlled by the master CPU card for monitoring and controlling said plurality of slave CPU cards at a hardware level.

Abstract: A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result, the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.

Abstract: The present invention provides an integrated VPN/firewall system that uses bath hardware (firmware) and software to optimize the efficiency of both VPN and firewall functions. The hardware portions of the VPN and firewall are designed in flexible and scalable layers to permit high-speed processing without sacrificing system security. The software portions are adapted to provide interfacing with hardware components, report and rules management control.