Patents by Inventor Jyu-Horng Shieh

Jyu-Horng Shieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250254956
    Abstract: A method includes forming a transistor comprising a source/drain region and a gate electrode, forming a source/drain contact plug over and electrically connecting to the source/drain region, forming a first inter-layer dielectric over the source/drain contact plug, forming an etch stop layer over the first inter-layer dielectric, etching the etch stop layer to form a first via opening, forming a second inter-layer dielectric over the first inter-layer dielectric, performing an etching process, so that the second inter-layer dielectric is etched to form a trench, and the first via opening in the etch stop layer is extended into the first inter-layer dielectric to reveal the source/drain contact plug, and filling the trench and the first via opening in common processes to form a metal line and a via, respectively.
    Type: Application
    Filed: April 22, 2025
    Publication date: August 7, 2025
    Inventors: Chien-Han Chen, Shih-Yu Chang, Chien-Chih Chiu, Huang-Ming Chen, Jyu-Horng Shieh
  • Patent number: 12341057
    Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Wen Wu, Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 12317751
    Abstract: An integrated circuit includes a metallization pattern having first and second conductive features, an etch stop layer over the metallization pattern, a memory device, a bottom electrode via, a third conductive feature, and a dielectric feature. The etch stop layer has first and second portions over the first and second conductive features, respectively. The bottom electrode via is in the first portion of the etch stop layer and electrically connecting the memory device over the first portion of the etch stop layer to the first conductive feature. The third conductive feature is in the second portion of the etch stop layer and electrically connected to the second conductive feature. The dielectric feature is between the first and second portions of the etch stop layer and in contact with sidewalls of the first and second portions of the etch stop layer.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh, Hui-Hsien Wei
  • Publication number: 20250132204
    Abstract: A method includes forming a first mandrel and a second mandrel over a dielectric layer, and forming a first spacer and a second spacer on the first mandrel and the second mandrel, respectively. The first spacer and the second spacer are next to each other with a space in between. The dielectric layer is etched to form an opening in the dielectric layer, with the opening being overlapped by the space, and with the first spacer and the second spacer being used as a part of an etching mask in the etching. A conductive material is filled into the opening. A planarization process is performed on the conductive material.
    Type: Application
    Filed: December 24, 2024
    Publication date: April 24, 2025
    Inventors: Yi-Nien Su, Jyu-Horng Shieh
  • Publication number: 20250133967
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Application
    Filed: December 24, 2024
    Publication date: April 24, 2025
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: 12237214
    Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Nien Su, Shu-Huei Suen, Jyu-Horng Shieh, Ru-Gun Liu
  • Publication number: 20250044708
    Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun LIU, Huicheng CHANG, Chia-Cheng CHEN, Jyu-Horng SHIEH, Liang-Yin CHEN, Shu-Huei SUEN, Wei-Liang LIN, Ya Hui CHANG, Yi-Nien SU, Yung-Sung YEN, Chia-Fong CHANG, Ya-Wen YEH, Yu-Tien SHEN
  • Patent number: 12218007
    Abstract: A method includes forming a first mandrel and a second mandrel over a dielectric layer, and forming a first spacer and a second spacer on the first mandrel and the second mandrel, respectively. The first spacer and the second spacer are next to each other with a space in between. The dielectric layer is etched to form an opening in the dielectric layer, with the opening being overlapped by the space, and with the first spacer and the second spacer being used as a part of an etching mask in the etching. A conductive material is filled into the opening. A planarization process is performed on the conductive material.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Nien Su, Jyu-Horng Shieh
  • Patent number: 12219879
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: 12217936
    Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.
    Type: Grant
    Filed: November 8, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Liang Pan, Bing-Hung Chen, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang, Jack Kuo-Ping Kuo
  • Patent number: 12183628
    Abstract: An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuan-Wei Huang, Yi-Nien Su, Yu-Yu Chen, Jyu-Horng Shieh
  • Patent number: 12153350
    Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Huicheng Chang, Chia-Cheng Chen, Jyu-Horng Shieh, Liang-Yin Chen, Shu-Huei Suen, Wei-Liang Lin, Ya Hui Chang, Yi-Nien Su, Yung-Sung Yen, Chia-Fong Chang, Ya-Wen Yeh, Yu-Tien Shen
  • Publication number: 20240379378
    Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu
  • Patent number: 12142520
    Abstract: Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yi-Nien Su, Jyu-Horng Shieh
  • Patent number: 12127489
    Abstract: An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Han-Ting Tsai, Jyu-Horng Shieh, Chung-Te Lin
  • Patent number: 12068167
    Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Wei Huang, Yu-Yu Chen, Jyu-Horng Shieh
  • Publication number: 20240251568
    Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.
    Type: Application
    Filed: April 4, 2024
    Publication date: July 25, 2024
    Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
  • Patent number: 11980040
    Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
  • Patent number: 11944017
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20240099150
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu