Patents by Inventor Jyun-Da Chen

Jyun-Da Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11964259
    Abstract: A catalyst composition for hydrogenating 4,4?-methylenedianiline derivatives is provided. The catalyst composition includes a carrier including aluminum oxide and magnesium oxide, a rhodium-ruthenium active layer loaded on the surface of the carrier, and a solvent including an organic amine. The weight percentage of magnesium oxide in the carrier is between 12% and 30%. A method for preparing 4,4?-methylene bis(cyclohexylamine) derivatives using the catalyst composition is also provided.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 23, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chao-Huang Chen, Jyun-Da Wu, Tzong-Shyan Lu, Ying-Chieh Lee
  • Patent number: 11961578
    Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: April 16, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jyun-Da Chen
  • Publication number: 20240079082
    Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Jyun-Da Chen
  • Patent number: 11621052
    Abstract: A method for testing a memory device includes the following steps of: generating a first refresh command to the memory device; storing a first refresh address information into a register of the memory device according to the first refresh command; reading out the first refresh address information according to a mode register read command; comparing the first refresh address information with an expectation address information to generate a comparison result; and generating a second refresh command to the memory device or screening out the memory device according to the comparison result.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: April 4, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jyun-Da Chen
  • Patent number: 11011251
    Abstract: A method of verifying a hard post package repair (hPPR) includes steps as follows. A predetermined data background is written into a partial array of a volatile memory. First data are read out from a target row of the partial array of the volatile memory. The volatile memory is commanded to perform the hPPR on the target row. The predetermined data background is written into the partial array of the volatile memory anew after the hPPR has been performed. Second data are read out from a target row of the partial array of the volatile memory. The first data are compared with the second data to verify whether the hPPR fails.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: May 18, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Jyun-Da Chen, Nung Yen