Patents by Inventor Jyun-Guan JHOU
Jyun-Guan JHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11894459Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.Type: GrantFiled: January 5, 2021Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chih Su, Ruey-Hsin Liu, Pei-Lun Wang, Jia-Rui Lee, Jyun-Guan Jhou
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Publication number: 20230040514Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.Type: ApplicationFiled: October 19, 2022Publication date: February 9, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsu-Hsiu PERNG, Yun-Chi WU, Chia-Chen CHANG, Cheng-Bo SHU, Jyun-Guan JHOU, Pei-Lun WANG
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Publication number: 20220384637Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsu-Hsiu PERNG, Yun-Chi WU, Chia-Chen CHANG, Cheng-Bo SHU, Jyun-Guan JHOU, Pei-Lun WANG
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Publication number: 20220384647Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.Type: ApplicationFiled: July 29, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chih SU, Ruey-Hsin LIU, Pei-Lun WANG, Jia-Rui LEE, Jyun-Guan JHOU
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Patent number: 11508843Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.Type: GrantFiled: May 27, 2021Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu-Hsiu Perng, Yun-Chi Wu, Chia-Chen Chang, Cheng-Bo Shu, Jyun-Guan Jhou, Pei-Lun Wang
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Publication number: 20220262908Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a gate electrode disposed on a substrate between a pair of source/drain regions. A dielectric layer is over the substrate. A field plate is disposed on the dielectric layer and laterally between the gate electrode and a first source/drain region in the pair of source/drain regions. The field plate comprises a first field plate layer and a second field plate layer. The second field plate layer extends along sidewalls and a bottom surface of the first field plate layer. The first and second field plate layers comprise a conductive material.Type: ApplicationFiled: May 3, 2022Publication date: August 18, 2022Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
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Patent number: 11335784Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a source region and a drain region within a substrate. A drift region is formed within the substrate such that the drift region is disposed laterally between the source region and the drain region. A first gate structure is formed over the drift region. An inter-level dielectric (ILD) layer is formed over the first gate structure. The ILD layers is patterned to define a field plate opening. A first field plate layer, a second field plate layer, and a third field plate layer are formed within the field plate opening.Type: GrantFiled: November 19, 2020Date of Patent: May 17, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
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Publication number: 20220029020Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.Type: ApplicationFiled: January 5, 2021Publication date: January 27, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chih SU, Ruey-Hsin LIU, Pei-Lun WANG, Jia-Rui LEE, Jyun-Guan JHOU
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Patent number: 11164970Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a gate structure disposed over a substrate between a source region and a drain region. A first inter-level dielectric (ILD) layer is disposed over the substrate and the gate structure and a second ILD layer is disposed over the first ILD layer. A field plate etch stop structure is between the first ILD layer and the second ILD layer. A field plate extends from an uppermost surface of the second ILD layer to the field plate etch stop structure. A plurality of conductive contacts extend from the uppermost surface of the second ILD layer to the source region and the drain region.Type: GrantFiled: July 9, 2019Date of Patent: November 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
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Publication number: 20210074820Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a source region and a drain region within a substrate. A drift region is formed within the substrate such that the drift region is disposed laterally between the source region and the drain region. A first gate structure is formed over the drift region. An inter-level dielectric (ILD) layer is formed over the first gate structure. The ILD layers is patterned to define a field plate opening. A first field plate layer, a second field plate layer, and a third field plate layer are formed within the field plate opening.Type: ApplicationFiled: November 19, 2020Publication date: March 11, 2021Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
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Patent number: 10861946Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode. The field plate and first gate electrode respectively include metal materials.Type: GrantFiled: May 21, 2019Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
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Publication number: 20200373395Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode. The field plate and first gate electrode respectively include metal materials.Type: ApplicationFiled: May 21, 2019Publication date: November 26, 2020Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
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Publication number: 20190334032Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a gate structure disposed over a substrate between a source region and a drain region. A first inter-level dielectric (ILD) layer is disposed over the substrate and the gate structure and a second ILD layer is disposed over the first ILD layer. A field plate etch stop structure is between the first ILD layer and the second ILD layer. A field plate extends from an uppermost surface of the second ILD layer to the field plate etch stop structure. A plurality of conductive contacts extend from the uppermost surface of the second ILD layer to the source region and the drain region.Type: ApplicationFiled: July 9, 2019Publication date: October 31, 2019Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
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Patent number: 10283604Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A first inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.Type: GrantFiled: July 31, 2015Date of Patent: May 7, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Szu-Hsien Lu, Hung-Che Liao, Kun-Tsang Chuang, Shih-Lu Hsu, Yu-Chu Lin, Jyun-Guan Jhou
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Patent number: 10141401Abstract: A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.Type: GrantFiled: May 26, 2017Date of Patent: November 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Lu Hsu, Ping-Pang Hsieh, Yu-Chu Lin, Jyun-Guan Jhou
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Publication number: 20170263464Abstract: A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.Type: ApplicationFiled: May 26, 2017Publication date: September 14, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Lu HSU, Ping-Pang HSIEH, Yu-Chu LIN, Jyun-Guan JHOU
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Patent number: 9666668Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a trench surrounding an active island of the substrate. The active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall. The inclined surface is inclined relative to the top surface at a first angle. The sidewall is inclined relative to the top surface at a second angle. The first angle is greater than the second angle. The semiconductor device structure includes an isolation structure in the trench. The semiconductor device structure includes a gate insulating layer over the top surface and the inclined surface. The semiconductor device structure includes a gate over the gate insulating layer and the isolation structure. The gate crosses the active island.Type: GrantFiled: October 27, 2015Date of Patent: May 30, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Lu Hsu, Ping-Pang Hsieh, Yu-Chu Lin, Jyun-Guan Jhou
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Publication number: 20170117355Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a trench surrounding an active island of the substrate. The active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall. The inclined surface is inclined relative to the top surface at a first angle. The sidewall is inclined relative to the top surface at a second angle. The first angle is greater than the second angle. The semiconductor device structure includes an isolation structure in the trench. The semiconductor device structure includes a gate insulating layer over the top surface and the inclined surface. The semiconductor device structure includes a gate over the gate insulating layer and the isolation structure. The gate crosses the active island.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Lu HSU, Ping-Pang HSIEH, Yu-Chu LIN, Jyun-Guan JHOU
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Publication number: 20170033047Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A fist inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.Type: ApplicationFiled: July 31, 2015Publication date: February 2, 2017Inventors: Szu-Hsien LU, Hung-Che LIAO, Kun-Tsang CHUANG, Shih-Lu HSU, Yu-Chu LIN, Jyun-Guan JHOU