Patents by Inventor Jyun-Hao CHANG
Jyun-Hao CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240020456Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.Type: ApplicationFiled: July 31, 2023Publication date: January 18, 2024Inventors: Chun-Yao Ku, Jyun-Hao Chang, Ming-Tao Yu, Wen-Hao Chen
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Patent number: 11755815Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect(LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.Type: GrantFiled: October 27, 2022Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Yao Ku, Jyun-Hao Chang, Ming-Tao Yu, Wen-Hao Chen
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Publication number: 20230230971Abstract: A method of forming an integrated circuit includes placing a first and a second standard cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height. Placing the first standard cell layout design includes placing a first set of pin layout patterns on a first layout level over a first set of gridlines, extending in a first direction, and having a first width in a second direction. Placing the second standard cell layout design includes placing a second set of pin layout patterns on the first layout level over a second set of gridlines, extending in the first direction, and having a second width in the second direction.Type: ApplicationFiled: March 27, 2023Publication date: July 20, 2023Inventors: Chun-Yao KU, Wen-Hao CHEN, Kuan-Ting CHEN, Ming-Tao YU, Jyun-Hao CHANG
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Patent number: 11675954Abstract: A method of designing a device includes identifying a pin to be inserted into a first layer of the device, wherein the first layer has a plurality of first routing tracks, and each of the plurality of first routing tracks extend in a first direction. The method further includes identifying a blocking shape on a second layer different from the first layer, wherein the second layer has a plurality of second routing tracks, and each of the plurality of second routing tracks extends in a second direction different from the first direction. The method further includes determining at least one candidate location for the pin in the first layer based on the plurality of first routing tracks of the first layer. The method further includes setting a location for the pin in the first layer based on the determined at least one candidate location.Type: GrantFiled: October 20, 2020Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Hsiung Chen, Jyun-Hao Chang, Ting-Wei Chiang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang
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Patent number: 11616055Abstract: A method of forming an integrated circuit includes generating a first and second standard cell layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height different from the first height. The second standard cell layout design is adjacent to the first standard cell layout design. Generating the first standard cell layout design includes generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width. Generating the second standard cell layout design includes generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width different from the first width.Type: GrantFiled: November 11, 2020Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Yao Ku, Wen-Hao Chen, Kuan-Ting Chen, Ming-Tao Yu, Jyun-Hao Chang
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Publication number: 20230058814Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect(LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.Type: ApplicationFiled: October 27, 2022Publication date: February 23, 2023Inventors: Chun-Yao Ku, Jyun-Hao Chang, Ming-Tao Yu, Wen-Hao Chen
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Patent number: 11514224Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.Type: GrantFiled: February 19, 2021Date of Patent: November 29, 2022Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chun-Yao Ku, Jyun-Hao Chang, Ming-Tao Yu, Wen-Hao Chen
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Patent number: 11281836Abstract: A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.Type: GrantFiled: April 5, 2021Date of Patent: March 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Ho Che Yu, Lee-Chung Lu, Ni-Wan Fan, Po-Hsiang Huang, Chi-Yu Lu, Jeo-Yen Lee
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Patent number: 11132488Abstract: A method of modifying a cell includes determining a number of pins in a maximum overlapped pin group region. The method further includes determining a number of routing tracks within a span region of the maximum overlapped pin group region. The method further includes comparing the number of pins and the number of routing tracks within the span region to determine a global tolerance of the cell. The method further includes increasing a length of at least one pin of the maximum overlapped pin group in response to the global tolerance failing to satisfy a predetermined threshold.Type: GrantFiled: January 29, 2020Date of Patent: September 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Hsiung Chen, Jyun-Hao Chang, Ting-Wei Chiang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang
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Publication number: 20210248300Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.Type: ApplicationFiled: February 19, 2021Publication date: August 12, 2021Inventors: Chun-Yao Ku, Jyun-Hao Chang, Ming-Tao Yu, Wen-Hao Chen
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Publication number: 20210224460Abstract: A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Fong-Yuan CHANG, Jyun-Hao CHANG, Sheng-Hsiung CHEN, Ho Che YU, Lee-Chung LU, Ni-Wan FAN, Po-Hsiang HUANG, Chi-Yu LU, Jeo-Yen LEE
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Patent number: 11030383Abstract: A method of forming an integrated device includes: providing a first via pillar file specifying a first via pillar; providing a second via pillar file specifying a second via pillar; arranging, by a processor, the first via pillar to electrically connect to a circuit cell in a first circuit; arranging an interconnecting path for electrical connection of the first via pillar to another circuit cell in the first circuit; arranging, by the processor, the second via pillar to replace the first via pillar when the first via pillar induces an electromigration (EM) phenomenon; re-routing the interconnecting path with replacement of the first via pillar to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.Type: GrantFiled: May 26, 2020Date of Patent: June 8, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Yao Ku, Wen-Hao Chen, Ming-Tao Yu, Shao-Huan Wang, Jyun-Hao Chang
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Patent number: 10970450Abstract: A semiconductor device comprising active areas and a structure. The active areas are formed as predetermined shapes on a substrate and arranged relative to a grid having first and second tracks which are substantially parallel to corresponding orthogonal first and second directions; The active areas are organized into instances of a first row having a first conductivity and a second row having a second conductivity. Each instance of the first row and of the second row includes a corresponding first and second number predetermined number of the first tracks. The structure has at least two contiguous rows including: at least one instance of the first row; and at least one instance of the second row. In the first direction, the instance(s) of the first row have a first width and the instance(s) of the second row a second width substantially different than the first width.Type: GrantFiled: October 12, 2017Date of Patent: April 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Ho Che Yu, Lee-Chung Lu, Ni-Wan Fan, Po-Hsiang Huang, Chi-Yu Lu, Jeo-Yen Lee
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Patent number: 10956650Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.Type: GrantFiled: February 11, 2020Date of Patent: March 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Yao Ku, Jyun-Hao Chang, Ming-Tao Yu, Wen-Hao Chen
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Publication number: 20210034807Abstract: A method of designing a device includes identifying a pin to be inserted into a first layer of the device, wherein the first layer has a plurality of first routing tracks, and each of the plurality of first routing tracks extend in a first direction. The method further includes identifying a blocking shape on a second layer different from the first layer, wherein the second layer has a plurality of second routing tracks, and each of the plurality of second routing tracks extends in a second direction different from the first direction. The method further includes determining at least one candidate location for the pin in the first layer based on the plurality of first routing tracks of the first layer. The method further includes setting a location for the pin in the first layer based on the determined at least one candidate location.Type: ApplicationFiled: October 20, 2020Publication date: February 4, 2021Inventors: Sheng-Hsiung CHEN, Jyun-Hao CHANG, Ting-Wei CHIANG, Fong-Yuan CHANG, I-Lun TSENG, Po-Hsiang HUANG
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Publication number: 20200411503Abstract: An integrated circuit includes a first region. The integrated circuit further includes a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first region or the second region, wherein the power structure includes a second conductive structure overlapping a boundary between the first region and the second region, the first conductive structure and the second conductive structure are aligned in a second direction different than the first direction, and the first conductive structure and the second conductive structure are separated from each other in the first direction.Type: ApplicationFiled: September 16, 2020Publication date: December 31, 2020Inventors: Fong-Yuan CHANG, Jyun-Hao CHANG, Sheng-Hsiung CHEN, Po-Hsiang HUANG, Lipen YUAN
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Patent number: 10797041Abstract: An integrated circuit includes a first region and a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a first via coupled to the first conductive structure. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first or second region. The power structure includes a second conductive structure extending in the first direction and overlapping a boundary between the first region and the second region. The first conductive structure and the second conductive structure are aligned in a second direction. The first conductive structure and the second conductive structure are separated from each other in the first direction by a distance greater than a minimum spacing requirement of the first conductive structure and the second conductive structure.Type: GrantFiled: November 29, 2018Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Lipen Yuan
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Patent number: 10777505Abstract: A method includes using a processor to placing a cell having a first conductive feature and a second conductive feature on an integrated circuit layout. A length of the first conductive feature is extended, by using the processor, to form a staggered configuration. A set of instructions for manufacturing an integrated circuit based upon the integrated circuit layout is generated, and the set of instructions is stored in a non-transitory machine readable storage medium.Type: GrantFiled: November 28, 2018Date of Patent: September 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Jyun-Hao Chang, Chun-Chen Chen
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Publication number: 20200285798Abstract: A method of forming an integrated device includes: providing a first via pillar file specifying a first via pillar; providing a second via pillar file specifying a second via pillar; arranging, by a processor, the first via pillar to electrically connect to a circuit cell in a first circuit; arranging an interconnecting path for electrical connection of the first via pillar to another circuit cell; arranging, by the processor, the second via pillar to replace the first via pillar when the first via pillar induces an electromigration (EM) phenomenon; re-routing the interconnecting path with replacement of the first via pillar to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.Type: ApplicationFiled: May 26, 2020Publication date: September 10, 2020Inventors: CHUN-YAO KU, WEN-HAO CHEN, MING-TAO YU, SHAO-HUAN WANG, JYUN-HAO CHANG
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Patent number: 10678991Abstract: A method of forming an integrated device includes: pre-storing a plurality of via pillars in a storage tool; arranging a first via pillar selected from the plurality of via pillars to electrically connect to a circuit cell in a first circuit; analyzing electromigration (EM) information of the first circuit to determine if the first via pillar induces an EM phenomenon; arranging a second via pillar selected from the plurality of via pillars to replace the first via pillar of the circuit cell to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.Type: GrantFiled: June 27, 2018Date of Patent: June 9, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Yao Ku, Wen-Hao Chen, Ming-Tao Yu, Shao-Huan Wang, Jyun-Hao Chang