Patents by Inventor Jyun-Hong Chen
Jyun-Hong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128179Abstract: A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.Type: ApplicationFiled: November 8, 2022Publication date: April 18, 2024Inventors: Jyun-Hong CHEN, Chi-Hai KUO, Pu-Ju LIN, Cheng-Ta KO
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Patent number: 11949043Abstract: A micro light-emitting diode is provided. The micro light-emitting diode includes a first-type semiconductor layer having a first doping type; a light-emitting layer over the first-type semiconductor layer; a first-type electrode over the first-type semiconductor layer; a second-type semiconductor layer having a second doping type over the light-emitting layer, wherein the second doping type is different from the first doping type; a second-type electrode over the second-type semiconductor layer; and a barrier layer under the first-type semiconductor layer and away from the first-type electrode and the second-type electrode, wherein the barrier layer includes a doped region having the second doping type.Type: GrantFiled: October 29, 2020Date of Patent: April 2, 2024Assignee: PLAYNITRIDE DISPLAY CO., LTD.Inventors: Yen-Chun Tseng, Tzu-Yang Lin, Jyun-De Wu, Fei-Hong Chen, Yi-Chun Shih
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Patent number: 11681851Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.Type: GrantFiled: November 19, 2021Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Venkata Sripathi Sasanka Pratapa, Jyun-Hong Chen, Wen-Hao Cheng
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Publication number: 20230178399Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.Type: ApplicationFiled: February 2, 2023Publication date: June 8, 2023Inventors: Peng-Ren Chen, Wen-Hao Cheng, Jyun-Hong Chen, Chien-Hui Chen
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Patent number: 11669957Abstract: A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.Type: GrantFiled: July 16, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Ren Chen, Yi-An Huang, Jyun-Hong Chen, Wei-Chung Hu, Wen-Hao Cheng, Shiang-Bau Wang, Yung-Jung Chang
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Patent number: 11600505Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.Type: GrantFiled: July 31, 2019Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Peng-Ren Chen, Wen-Hao Cheng, Jyun-Hong Chen, Chien-Hui Chen
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Publication number: 20220367396Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
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Patent number: 11469198Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.Type: GrantFiled: March 14, 2019Date of Patent: October 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Ho Tsai, Jyun-Hong Chen, Chun-Chen Liu, Yu-Nu Hsu, Peng-Ren Chen, Wen-Hao Cheng, Chi-Ming Tsai
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Publication number: 20220075924Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.Type: ApplicationFiled: November 19, 2021Publication date: March 10, 2022Inventors: Venkata Sripathi Sasanka Pratapa, Jyun-Hong Chen, Wen-Hao Cheng
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Patent number: 11182532Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.Type: GrantFiled: March 2, 2020Date of Patent: November 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Venkata Sripathi Sasanka Pratapa, Jyun-Hong Chen, Wen-Hao Cheng
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Publication number: 20210342994Abstract: A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Inventors: Peng-Ren CHEN, Yi-An HUANG, Jyun-Hong CHEN, Wei-Chung HU, Wen-Hao CHENG, Shiang-Bau WANG, Yung-Jung CHANG
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Patent number: 11094057Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.Type: GrantFiled: August 3, 2020Date of Patent: August 17, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Ren Chen, Shiang-Bau Wang, Wen-Hao Cheng, Yung-Jung Chang, Wei-Chung Hu, Yi-An Huang, Jyun-Hong Chen
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Publication number: 20210019465Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.Type: ApplicationFiled: March 2, 2020Publication date: January 21, 2021Inventors: Venkata Sripathi Sasanka Pratapa, Jyun-Hong Chen, Wen-Hao Cheng
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Publication number: 20200364844Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.Type: ApplicationFiled: August 3, 2020Publication date: November 19, 2020Inventors: Peng-Ren CHEN, Shiang-Bau WANG, Wen-Hao CHENG, Yung-Jung CHANG, Wei-Chung HU, Yi-An HUANG, Jyun-Hong CHEN
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Patent number: 10762621Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.Type: GrantFiled: May 1, 2019Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Peng-Ren Chen, Shiang-Bau Wang, Wen-Hao Cheng, Yung-Jung Chang, Wei-Chung Hu, Yi-An Huang, Jyun-Hong Chen
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Publication number: 20200133959Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.Type: ApplicationFiled: July 31, 2019Publication date: April 30, 2020Inventors: Peng-Ren Chen, Wen-Hao Cheng, Jyun-Hong Chen, Chien-Hui Chen
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Patent number: 10538486Abstract: The present invention relates to a hydroxamic acid-based contrast agent containing an isotope of fluorine, which comprises a compound having a structure of Formula (III): wherein R1 represents radioactive fluorine-18 (18F) or isotope fluorine-19 (19F), and R2 represents hydroxyamine —(NH)OH. The hydroxamic acid-based contrast agent containing an isotope of fluorine provided in the present invention has the capability of selectively inhibiting histone deacetylase (HDAC) subtypes 8/6/3, and specifically targets to the focus of spinocerebellar ataxia with over-activation of HDAC. By labeling with the radioisotope fluorine-18, a positron emission tomography (PET) image is obtained with the hydroxamic acid-based contrast agent containing radioisotope fluorine-18, whereby spinocerebellar ataxia is effectively detected.Type: GrantFiled: October 27, 2017Date of Patent: January 21, 2020Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN. R.O.CInventors: Mei-Hui Wang, Chia-Yu Hu, Mao-Chi Weng, Jyun-Hong Chen, Chun-Hung Yang, Hung-Man Yu
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Publication number: 20200020655Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.Type: ApplicationFiled: March 14, 2019Publication date: January 16, 2020Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
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Publication number: 20190259140Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Inventors: Peng-Ren CHEN, Shiang-Bau WANG, Wen-Hao CHENG, Yung-Jung CHANG, Wei-Chung HU, Yi-An HUANG, Jyun-Hong CHEN
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Patent number: 10304178Abstract: Methods and systems for diagnosing semiconductor wafer are provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image includes a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.Type: GrantFiled: September 18, 2015Date of Patent: May 28, 2019Assignee: TAIWAN SEMICONDUCTOR MANFACTURING COMPANY, LTD.Inventors: Peng-Ren Chen, Shiang-Bau Wang, Wen-Hao Cheng, Yung-Jung Chang, Wei-Chung Hu, Yi-An Huang, Jyun-Hong Chen