Abstract: A ferroelectric memory structure including a substrate, first and second conductive lines, first and second dielectric layers, a channel pillar, a gate pillar, and a ferroelectric material layer is provided. The first conductive line is located on the substrate. The first dielectric layer is located on the first conductive line. The channel pillar is located on the first conductive line and in the first dielectric layer. The second conductive line is located on the first dielectric layer and the channel pillar. The gate pillar passes through the second conductive line and is located in the channel pillar. The second dielectric layer is located between the gate pillar and the first conductive line, between the gate pillar and the channel pillar, and between the gate pillar and the second conductive line. The ferroelectric material layer is located between the gate pillar and the second dielectric layer.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

Abstract: A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.

Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.

Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

Abstract: A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.

Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.

Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.

Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.