Abstract: The present disclosure provides a method for preparing a memory device. The method includes forming a doped region in a semiconductor substrate, and forming a word line across the doped region such that a first source/drain region and a second source/drain region are formed in the doped region and at opposite sides of the word line. The method also includes forming a bit line over and electrically connected to the first source/drain region, and forming a capacitor over and electrically connected to the second source/drain region. The formation of the capacitor includes forming a bottom electrode, forming a capacitor dielectric structure over the bottom electrode, and forming a top electrode over the capacitor dielectric structure.

Abstract: A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and at opposite sides of the word line, a bit line disposed over and electrically connected to the first source/drain region, and a capacitor disposed over and electrically connected to the second source/drain region. The capacitor includes a bottom electrode, a top electrode, and a capacitor dielectric structure disposed between them. The capacitor dielectric structure includes a first metal oxide layer, a second metal oxide layer disposed over the first metal oxide layer, and a third metal oxide layer disposed over the second metal oxide layer. The first, the second and the third metal oxide layer include materials that are different from each other.

Abstract: A method of forming a capacitor structure includes following operations. A first electrode is formed. A hafnium-zirconium oxide (HZO) layer is formed over the first electrode under a first temperature. An interface dielectric layer is formed over the HZO layer under a second temperature greater than the first temperature. A second electrode is formed over the interface dielectric layer. The HZO layer and the interface dielectric layer are annealed.

Abstract: The present application provides a storage capacitor with multiple dielectrics. The storage capacitor includes a lower electrode, an upper electrode, a first dielectric layer, a second dielectric layer and a third dielectric layer. The first dielectric layer covers the lower electrode, the second dielectric layer is disposed on the first dielectric layer, and the third dielectric layer is disposed on the second dielectric layer. The upper electrode is disposed on the third dielectric layer.

Abstract: The present application provides a method of fabricating a storage capacitor. The method includes steps of forming a lower electrode; depositing a first dielectric layer covering the lower electrode; depositing a second dielectric layer on the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; and forming an upper electrode on the third dielectric layer.

Abstract: A method of forming a capacitor structure includes following operations. A first electrode is formed. A hafnium-zirconium oxide (HZO) layer is formed over the first electrode under a first temperature. An interface dielectric layer is formed over the HZO layer under a second temperature greater than the first temperature. A second electrode is formed over the interface dielectric layer. The HZO layer and the interface dielectric layer are annealed.

Abstract: A method of forming a capacitor structure includes following operations. A first electrode is formed. A hafnium-zirconium oxide (HZO) layer is formed over the first electrode under a first temperature. An interface dielectric layer is formed over the HZO layer under a second temperature greater than the first temperature. A second electrode is formed over the interface dielectric layer. The HZO layer and the interface dielectric layer are annealed.