Patents by Inventor Jyun-Liang WU

Jyun-Liang WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip package and manufacturing method thereof
    Patent number: 9947716
    Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 17, 2018
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Hsiao-Lan Yeh, Chia-Sheng Lin, Yi-Ming Chang, Po-Han Lee, Hui-Hsien Wu, Jyun-Liang Wu, Shu-Ming Chang, Yu-Lung Huang, Chien-Min Lin
  • Chip package and manufacturing method thereof
    Patent number: 9875912
    Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 23, 2018
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Hsiao-Lan Yeh, Chia-Sheng Lin, Yi-Ming Chang, Po-Han Lee, Hui-Hsien Wu, Jyun-Liang Wu
  • CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170148844
    Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.
    Type: Application
    Filed: November 22, 2016
    Publication date: May 25, 2017
    Inventors: Yen-Shih HO, Hsiao-Lan YEH, Chia-Sheng LIN, Yi-Ming CHANG, Po-Han LEE, Hui-Hsien WU, Jyun-Liang WU, Shu-Ming CHANG, Yu-Lung HUANG, Chien-Min LIN
  • CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170148694
    Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.
    Type: Application
    Filed: November 21, 2016
    Publication date: May 25, 2017
    Inventors: Yen-Shih HO, Hsiao-Lan YEH, Chia-Sheng LIN, Yi-Ming CHANG, Po-Han LEE, Hui-Hsien WU, Jyun-Liang WU
  • CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170110495
    Abstract: A chip package includes a chip, a dam element, and a height-increasing element. The chip has an image sensing area, a first surface, and a second surface opposite to the first surface. The image sensing area is located on the first surface of the chip. The dam element is located on the first surface of the chip and surrounds the image sensing area. The height-increasing element is located on the dam element, such that the dam element is between the height-increasing element and the chip.
    Type: Application
    Filed: September 27, 2016
    Publication date: April 20, 2017
    Inventors: Jyun-Liang WU, Chia-Sheng LIN, Po-Han LEE, Yen-Shih HO