Abstract: A first integrated circuit (IC) die includes a first substrate. A second IC die includes a second substrate. At least one of the first substrate or the second substrate has a first surface orientation. The first IC die is spaced apart from the second IC die. A third die electrically interconnects the first IC die to the second IC die. The third die includes a third substrate having a second surface orientation. The second surface orientation is different from the first surface orientation.

Abstract: A semiconductor structure includes an interposer having a first planar surface, a set of non-horizontal surfaces having a top periphery that are adjoined to a periphery of the first planar surface, and a frame-shaped surface adjoined to a bottom periphery of the set of non-horizontal surfaces, sidewalls adjoined to the frame-shaped surface, and a second planar surface adjoined to the sidewalls; at least one semiconductor die attached to the interposer through a respective array of solder material portions; and an underfill material portion located between the interposer and the at least one semiconductor die and contacting a portion of the first planar surface.

Abstract: Methods for improving joinder between a surface-mount package and a printed circuit board are disclosed. The warpage at a corner of the surface-mount package and at a corresponding corner of a joint area on the printed circuit board are measured to determine the degree of mismatch. A mini-pad is applied to the corner between the surface-mount package and the joint area on the printed circuit board. The thickness of the mini-pad pushes against the surface-mount package and the printed circuit board, reducing the degree of mismatch below a critical dimension of a ball grid array of the surface-mount package. The surface-mount package can then be soldered to the joint area, reducing or preventing the formation of solder bridges and short circuits.

Abstract: A chip-on-wafer-on-substrate (CoWoS) semiconductor assembly is formed which includes a chip-on-wafer (CoW) sub-assembly of integrated circuit (IC) dies mounted on an interposer, which is in turn mounted on a package substrate with a top metallization stack and a bottom metallization stack using bonding bumps connecting the backside of the interposer and the front side of the package substrate. The bonding bumps provide electrical connections between the ends of through-vias exposed at the backside of the interposer and the top metallization stack of the package substrate. The likelihood of certain failure mechanisms that can adversely affect CoWoS yield are reduced or eliminated by ensuring a total metal thickness of the top metallization stack is greater than a total metal thickness of the bottom metallization stack, but not so much greater as to induce cracking of the underfill material during curing thereof.

Abstract: The present disclosure provides a semiconductor structure, including providing a first chip, disposing a first copper layer having a first thickness over a first side of the first chip, and disposing a first solder having a second thickness over the first copper layer, wherein a ratio of the second thickness and the first thickness is in a range of from about 2 to about 3.5.

Abstract: The present disclosure provides a semiconductor structure, including providing a first chip, disposing a first copper layer having a first thickness over a first side of the first chip, and disposing a first solder having a second thickness over the first copper layer, wherein a ratio of the second thickness and the first thickness is in a range of from about 2 to about 3.5.

Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Abstract: A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.

Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Abstract: A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.

Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.