Patents by Inventor Jyun-Lin Wu

Jyun-Lin Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006659
    Abstract: Methods for reducing warpage and increasing the effectiveness of hybrid bond void testing are disclosed. A semiconductor package has a first side and a second side, with a dummy bond pad located on the second side, and at least one metal-containing layer between the first side and the second side (for example a redistribution layer). A warpage control structure is provided in the semiconductor package that extends from the first side into the semiconductor package, and is aligned with the dummy bond pad. The warpage control structure is made of a low-density filling. This relieves stress that causes/increases warpage. When a hybrid bond is formed between the semiconductor package and another semiconductor package, the warpage control structure maximizes acoustic wave penetration for testing the quality of the hybrid bond at the dummy bond pad.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Ji-Feng Ying, Xuewen Tang, Wen-Hsien Chuang, Jyun-Lin Wu, Chia Wei Chang
  • Publication number: 20240389239
    Abstract: Methods for improving joinder between a surface-mount package and a printed circuit board are disclosed. The warpage at a corner of the surface-mount package and at a corresponding corner of a joint area on the printed circuit board are measured to determine the degree of mismatch. A mini-pad is applied to the corner between the surface-mount package and the joint area on the printed circuit board. The thickness of the mini-pad pushes against the surface-mount package and the printed circuit board, reducing the degree of mismatch below a critical dimension of a ball grid array of the surface-mount package. The surface-mount package can then be soldered to the joint area, reducing or preventing the formation of solder bridges and short circuits.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Hsien-Wen Liu, Shih-Ting Hung, Jyun-Lin Wu, Yao-Chun Chuang, Yinlung Lu
  • Publication number: 20240355804
    Abstract: A chip-on-wafer-on-substrate (CoWoS) semiconductor assembly is formed which includes a chip-on-wafer (CoW) sub-assembly of integrated circuit (IC) dies mounted on an interposer, which is in turn mounted on a package substrate with a top metallization stack and a bottom metallization stack using bonding bumps connecting the backside of the interposer and the front side of the package substrate. The bonding bumps provide electrical connections between the ends of through-vias exposed at the backside of the interposer and the top metallization stack of the package substrate. The likelihood of certain failure mechanisms that can adversely affect CoWoS yield are reduced or eliminated by ensuring a total metal thickness of the top metallization stack is greater than a total metal thickness of the bottom metallization stack, but not so much greater as to induce cracking of the underfill material during curing thereof.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 24, 2024
    Inventors: Chia-Wei Chang, Ju-Min Chen, Jyun-Lin Wu, Yao-Chun Chuang
  • Patent number: 12068300
    Abstract: A chip-on-wafer-on-substrate (CoWoS) semiconductor assembly is formed which includes a chip-on-wafer (CoW) sub-assembly of integrated circuit (IC) dies mounted on an interposer, which is in turn mounted on a package substrate with a top metallization stack and a bottom metallization stack using bonding bumps connecting the backside of the interposer and the front side of the package substrate. The bonding bumps provide electrical connections between the ends of through-vias exposed at the backside of the interposer and the top metallization stack of the package substrate. The likelihood of certain failure mechanisms that can adversely affect CoWoS yield are reduced or eliminated by ensuring a total metal thickness of the top metallization stack is greater than a total metal thickness of the bottom metallization stack, but not so much greater as to induce cracking of the underfill material during curing thereof.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chang, Ju-Min Chen, Jyun-Lin Wu, Yao-Chun Chuang
  • Publication number: 20240094104
    Abstract: An embodiment interfacial bonding test structure may include a first substrate having a first planar surface, a second substrate having a second planar surface that is parallel to the first planar surface, a first semiconductor die, and a second semiconductor die, each semiconductor die bonded between the first substrate and the second substrate thereby forming a sandwich structure. The first semiconductor die and the second semiconductor die may be bonded to the first surface with a first adhesive and may be bonded to the second surface with a second adhesive. The first semiconductor die and the second semiconductor die may be displaced from one another by a first separation along a direction parallel to the first planar surface and the second planar surface. The second substrate may include a notch having an area that overlaps with an area of the first separation in a plan view.
    Type: Application
    Filed: April 20, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Sheng Lin, Jyun-Lin Wu, Yao-Chun Chuang, Chin-Fu Kao
  • Publication number: 20240071974
    Abstract: A semiconductor package includes a substrate and at least one integrated circuit (IC) die. Substrate solder resist has substrate solder resist openings exposing substrate bonding pads of the bonding surface of the substrate, and die solder resist has aligned die solder resist openings exposing die bonding pads of the bonding surface of the IC die. A ball grid array (BGA) electrically connects the die bonding pads with substrate bonding pads via the die solder resist openings and the substrate solder resist openings. The die solder resist openings include a subset A of the die solder resist openings in a region A of the bonding surface of the IC die and a subset B of the die solder resist openings in a region B of the bonding surface of the IC die. The die solder resist openings of subset A are larger than those of subset B.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Yu-Sheng Lin, Chen-Nan Chiu, Jyun-Lin Wu, Yao-Chun Chuang
  • Publication number: 20240055354
    Abstract: A first integrated circuit (IC) die includes a first substrate. A second IC die includes a second substrate. At least one of the first substrate or the second substrate has a first surface orientation. The first IC die is spaced apart from the second IC die. A third die electrically interconnects the first IC die to the second IC die. The third die includes a third substrate having a second surface orientation. The second surface orientation is different from the first surface orientation.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 15, 2024
    Inventors: Yu-Sheng Lin, Chin-Fu Kao, Tsung-Yang Hsieh, Jyun-Lin Wu, Yao-Chun Chuang
  • Publication number: 20240030076
    Abstract: A semiconductor structure includes an interposer having a first planar surface, a set of non-horizontal surfaces having a top periphery that are adjoined to a periphery of the first planar surface, and a frame-shaped surface adjoined to a bottom periphery of the set of non-horizontal surfaces, sidewalls adjoined to the frame-shaped surface, and a second planar surface adjoined to the sidewalls; at least one semiconductor die attached to the interposer through a respective array of solder material portions; and an underfill material portion located between the interposer and the at least one semiconductor die and contacting a portion of the first planar surface.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Inventors: Yu-Sheng Lin, Hsin-Hsien Lee, Jyun-Lin Wu, Yao-Chun Chuang
  • Publication number: 20230422403
    Abstract: Methods for improving joinder between a surface-mount package and a printed circuit board are disclosed. The warpage at a corner of the surface-mount package and at a corresponding corner of a joint area on the printed circuit board are measured to determine the degree of mismatch. A mini-pad is applied to the corner between the surface-mount package and the joint area on the printed circuit board. The thickness of the mini-pad pushes against the surface-mount package and the printed circuit board, reducing the degree of mismatch below a critical dimension of a ball grid array of the surface-mount package. The surface-mount package can then be soldered to the joint area, reducing or preventing the formation of solder bridges and short circuits.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Hsien-Wen Liu, Shih-Ting Hung, Jyun-Lin Wu, Yao-Chun Chuang, Yinlung Lu
  • Publication number: 20230275077
    Abstract: A chip-on-wafer-on-substrate (CoWoS) semiconductor assembly is formed which includes a chip-on-wafer (CoW) sub-assembly of integrated circuit (IC) dies mounted on an interposer, which is in turn mounted on a package substrate with a top metallization stack and a bottom metallization stack using bonding bumps connecting the backside of the interposer and the front side of the package substrate. The bonding bumps provide electrical connections between the ends of through-vias exposed at the backside of the interposer and the top metallization stack of the package substrate. The likelihood of certain failure mechanisms that can adversely affect CoWoS yield are reduced or eliminated by ensuring a total metal thickness of the top metallization stack is greater than a total metal thickness of the bottom metallization stack, but not so much greater as to induce cracking of the underfill material during curing thereof.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Inventors: Chia-Wei Chang, Ju-Min Chen, Jyun-Lin Wu, Yao-Chun Chuang
  • Patent number: 10847492
    Abstract: The present disclosure provides a semiconductor structure, including providing a first chip, disposing a first copper layer having a first thickness over a first side of the first chip, and disposing a first solder having a second thickness over the first copper layer, wherein a ratio of the second thickness and the first thickness is in a range of from about 2 to about 3.5.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jyun-Lin Wu, Liang-Chen Lin, Shiang-Ruei Su
  • Publication number: 20190393186
    Abstract: The present disclosure provides a semiconductor structure, including providing a first chip, disposing a first copper layer having a first thickness over a first side of the first chip, and disposing a first solder having a second thickness over the first copper layer, wherein a ratio of the second thickness and the first thickness is in a range of from about 2 to about 3.5.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Jyun-Lin WU, Liang-Chen LIN, Shiang-Ruei SU
  • Patent number: 10014252
    Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Cheng Chang, Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu, Jyun-Lin Wu, Hsien-Pin Hu
  • Patent number: 9711474
    Abstract: A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Gia-Her Lu, Liang-Chen Lin, Tung-Chin Yeh, Jyun-Lin Wu, Tung-Jiun Wu
  • Publication number: 20160315050
    Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.
    Type: Application
    Filed: July 1, 2016
    Publication date: October 27, 2016
    Inventors: Shih-Cheng Chang, Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu, Jyun-Lin Wu, Hsien-Pin Hu
  • Patent number: 9385079
    Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Cheng Chang, Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu, Jyun-Lin Wu, Hsien-Pin Hu
  • Publication number: 20160086902
    Abstract: A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Inventors: GIA-HER LU, LIANG-CHEN LIN, TUNG-CHIN YEH, JYUN-LIN WU, TUNG-JIUN WU
  • Publication number: 20150214150
    Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.
    Type: Application
    Filed: July 17, 2014
    Publication date: July 30, 2015
    Inventors: Shih-Cheng Chang, Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu, Jyun-Lin Wu, Hsien-Pin Hu