Abstract: A substrate structure is provided, which includes a substrate having a plurality of conductors and at least a receiving space formed on a surface of the substrate with the receiving space free from penetrating the substrate. During an encapsulating process, an encapsulant can be filled in the receiving space so as to strengthen the bonding between the substrate and the encapsulant, thereby preventing delamination from occurring therebetween.

Abstract: A chip structure is provided, which includes: a substrate having a plurality of conductive pads formed on a surface thereof; a first copper layer formed on each of the conductive pads; a nickel layer formed on the first copper layer; a second copper layer formed on the nickel layer; and a tin layer formed on the second copper layer, thereby effectively reducing stresses.

Abstract: A semiconductor interposer is provided, which includes: a substrate body having a surface defined with an inner area and a peripheral area around the inner area; a plurality of conductive posts embedded in the substrate body and each having one end exposed from the surface of the substrate body; a passivation layer formed on the surface of the substrate body and having a peripheral portion formed in the peripheral area, a plurality of ring-shaped portions formed around peripheries of the exposed ends of the conductive posts in the inner area and a plurality of strip-shaped portions formed between the ring-shaped portions for connecting the ring-shaped portions; and a UBM layer formed on the exposed end of each of the conductive posts and extending on the ring-shaped portion around the periphery of the exposed end of the conductive post, thereby effectively reducing stresses to prevent warping of the semiconductor interposer.

Abstract: A chip structure is provided, which includes: a substrate having a plurality of conductive pads formed on a surface thereof; a first copper layer formed on each of the conductive pads; a nickel layer formed on the first copper layer; a second copper layer formed on the nickel layer; and a tin layer formed on the second copper layer, thereby effectively reducing stresses.

Abstract: A semiconductor interposer is provided, which includes: a substrate body having a surface defined with an inner area and a peripheral area around the inner area; a plurality of conductive posts embedded in the substrate body and each having one end exposed from the surface of the substrate body; a passivation layer formed on the surface of the substrate body and having a peripheral portion formed in the peripheral area, a plurality of ring-shaped portions formed around peripheries of the exposed ends of the conductive posts in the inner area and a plurality of strip-shaped portions formed between the ring-shaped portions for connecting the ring-shaped portions; and a UBM layer formed on the exposed end of each of the conductive posts and extending on the ring-shaped portion around the periphery of the exposed end of the conductive post, thereby effectively reducing stresses to prevent warping of the semiconductor interposer.