Patents by Inventor JYUN-WEI PU

JYUN-WEI PU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240121028
    Abstract: The present disclosure discloses a data receiving apparatus and a data receiving method having blind deconvolution mechanism. A descrambling circuit descrambles received data according to an antenna assumption and N data position assumptions within a transmission period to generate N groups of soft-bit data. A soft-bit processing circuit retrieves bit position data to determine non-variable bit positions and variable bit positions. N circular buffers of a storage circuit store and superimpose the N groups of soft-bit data corresponding to N data position assumptions in a circular manner to generate N groups of superimposed results and keep the data corresponding to the non-variable bit positions. A post-processing circuit performs de-interleaving and decoding on the N groups of superimposed results to generate N groups of decoded results to perform redundancy check thereon. When one decoded results passes the redundancy check, the soft-bit processing circuit stops performing the blind deconvolution process.
    Type: Application
    Filed: June 16, 2023
    Publication date: April 11, 2024
    Inventors: FENG-XIANG WANG, MING-YUE YOU, JYUN-WEI PU, JIA-YI ZHUANG
  • Publication number: 20220116140
    Abstract: The present invention discloses a data decoding circuit. A data reforming circuit receives encoded data encoded by using tail-biting convolutional code to identify a first unknown bit section, a known bit section and a second unknown bit section in an order to further connect the second unknown bit section and the first unknown bit section in series to generate data to be decoded. A decoding circuit decodes the data to be decoded by using Viterbi algorithm and at least one piece of known bit information to generate a decoded result that includes a second decoded bit section and a first decoded bit section respectively corresponding to the second unknown bit section and the first unknown bit section. A data restoring circuit connects the first decoded bit section, a known decoded bit section corresponding to the known bit section and the second decoded bit section in series to generate decoded data.
    Type: Application
    Filed: June 11, 2021
    Publication date: April 14, 2022
    Inventors: FENG-XIANG WANG, JYUN-WEI PU
  • Patent number: 11290132
    Abstract: The present invention discloses a data decoding circuit. A data reforming circuit receives encoded data encoded by using tail-biting convolutional code to identify a first unknown bit section, a known bit section and a second unknown bit section in an order to further connect the second unknown bit section and the first unknown bit section in series to generate data to be decoded. A decoding circuit decodes the data to be decoded by using Viterbi algorithm and at least one piece of known bit information to generate a decoded result that includes a second decoded bit section and a first decoded bit section respectively corresponding to the second unknown bit section and the first unknown bit section. A data restoring circuit connects the first decoded bit section, a known decoded bit section corresponding to the known bit section and the second decoded bit section in series to generate decoded data.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: March 29, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Feng-Xiang Wang, Jyun-Wei Pu
  • Patent number: 9859929
    Abstract: The present invention includes a noise variance estimation circuit for wireless communication. An embodiment of the noise variance estimation circuit includes: a first estimation unit operable to generate a first estimation signal according to a reception signal and a reference signal in which the reception signal is derived from the equivalent of the reference signal; a first noise reduction unit operable to generate a first noise reduction signal by performing a first noise reduction process to the first estimation signal; a second estimation unit operable to generate a second estimation signal according to the difference between the first estimation signal and the first noise reduction signal; and a second noise reduction unit operable to execute a noise reduction adjustment according to the second estimation signal and perform a second noise reduction process to the first estimation signal in which the noise reduction adjustment affects the second noise reduction process.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: January 2, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jyun-Wei Pu, Chung-Yao Chang
  • Publication number: 20170207804
    Abstract: The present invention includes a noise variance estimation circuit for wireless communication. An embodiment of the noise variance estimation circuit includes: a first estimation unit operable to generate a first estimation signal according to a reception signal and a reference signal in which the reception signal is derived from the equivalent of the reference signal; a first noise reduction unit operable to generate a first noise reduction signal by performing a first noise reduction process to the first estimation signal; a second estimation unit operable to generate a second estimation signal according to the difference between the first estimation signal and the first noise reduction signal; and a second noise reduction unit operable to execute a noise reduction adjustment according to the second estimation signal and perform a second noise reduction process to the first estimation signal in which the noise reduction adjustment affects the second noise reduction process.
    Type: Application
    Filed: November 25, 2016
    Publication date: July 20, 2017
    Inventors: JYUN-WEI PU, CHUNG-YAO CHANG