Abstract: A frequency detection device for a clock signal and a detection method thereof are provided. The frequency detection device includes a pulse signal generator, a sampling signal generator, a delay device, and a sampling circuit. The pulse signal generator detects a plurality of transition edges of the clock signal and generates a pulse signal according to the transition edges of the clock signal. The sampling signal generator generates a sampling signal based on a command signal according to pluses of the pulse signal. The delay device delays the command signal to generate a delayed command signal. The sampling circuit samples the delayed command signal according to the sampling signal to generate a detection result.

Abstract: A frequency detection device for a clock signal and a detection method thereof are provided. The frequency detection device includes a pulse signal generator, a sampling signal generator, a delay device, and a sampling circuit. The pulse signal generator detects a plurality of transition edges of the clock signal and generates a pulse signal according to the transition edges of the clock signal. The sampling signal generator generates a sampling signal based on a command signal according to pluses of the pulse signal. The delay device delays the command signal to generate a delayed command signal. The sampling circuit samples the delayed command signal according to the sampling signal to generate a detection result.

Abstract: A non-volatile memory device, including a non-volatile memory cell array, a sense amplifier, a random access memory (RAM), and a buffer circuit, is provided. The sense amplifier is configured to generate readout data. The RAM is configured to store write-in data. The buffer circuit generates a detection result according to target data and the readout data, and writes the detection result to the RAM.

Abstract: A non-volatile memory device, including a non-volatile memory cell array, a sense amplifier, a random access memory (RAM), and a buffer circuit, is provided. The sense amplifier is configured to generate readout data. The RAM is configured to store write-in data. The buffer circuit generates a detection result according to target data and the readout data, and writes the detection result to the RAM.

Abstract: A voltage regulator device and a control method thereof are provided. The voltage regulator device includes a voltage regulator and a path switch. The voltage regulator includes an output node and a voltage divider circuit. The output node is used to generate a control voltage. The voltage divider circuit generates an overshoot reference voltage according to an input voltage. A first node of the path switch is coupled to the output node, a second node of the path switch is coupled to a reference voltage node, and a control node of the path switch receives the overshoot reference voltage. When the control voltage is greater than the sum of the overshoot reference voltage and a threshold voltage of the path switch, the path switch is turned on to direct a charge at the output node to the reference voltage node.

Abstract: A power on reset circuit includes a first inverting circuit, a second inverting circuit, a charging apparatus, an output buffer, a current drainer, and a first capacitor. The first inverting circuit and the second inverting circuit are coupled between a voltage detection end and a signal control end in opposite directions. The current drainer drains a current from the voltage detection end according to a power voltage and a voltage on the signal control end. The charging apparatus charges the voltage detection end according to the voltage on the signal control end. The output buffer generates a reset signal according to the voltage on the signal control end.

Abstract: A power on reset circuit includes a first inverting circuit, a second inverting circuit, a charging apparatus, an output buffer, a current drainer, and a first capacitor. The first inverting circuit and the second inverting circuit are coupled between a voltage detection end and a signal control end in opposite directions. The current drainer drains a current from the voltage detection end according to a power voltage and a voltage on the signal control end. The charging apparatus charges the voltage detection end according to the voltage on the signal control end. The output buffer generates a reset signal according to the voltage on the signal control end.

Abstract: A power-on reset signal generating apparatus and a voltage detection circuit thereof are provided. The voltage detection circuit includes a latch circuit, a pre-charge circuit, a pull-down switch and an output stage circuit. The pull-down circuit is turned on or cut off according to the power-on reset signal. The pre-charge circuit operates a pre-charge action according to a power-on reset signal or a power supply voltage. The output stage circuit receives the power supply voltage, based on the power supply voltage, generates a detection output voltage according to an input end of the inverter and the power-on reset signal.