Abstract: A terminal 20 includes a terminal connection portion 21 connected to a counterpart terminal and a board connection portion 24 connected to a conductive path 13 of a board 11. The board connection portion 24 has a plate shape portion 25 that is a plate shape. The plate shape portion is disposed behind the terminal connection portion 21 and is soldered to the conductive path 13 of the board 11. The board connection portion has a plate-shape first projection walls 28A to 28D that are bent from edge portions of a lateral direction side of the plate shape portion 25 and that project to an opposite side to the board 11 side. The plate shape portion 25 and the first projection walls 28A to 28D have a plating layer 37 that is formed on a plate surface of the plate shape portion and the first projection walls.

Abstract: A terminal 20 includes a terminal connection portion 21 connected to a counterpart terminal and a board connection portion 24 connected to a conductive path 13 of a board 11. The board connection portion 24 has a plate shape portion 25 that is a plate shape. The plate shape portion is disposed behind the terminal connection portion 21 and is soldered to the conductive path 13 of the board 11. The board connection portion has a plate-shape first projection walls 28A to 28D that are bent from edge portions of a lateral direction side of the plate shape portion 25 and that project to an opposite side to the board 11 side. The plate shape portion 25 and the first projection walls 28A to 28D have a plating layer 37 that is formed on a plate surface of the plate shape portion and the first projection walls.

Abstract: A method of driving a matrix-type liquid crystal display device utilizing a liquid crystal layer sandwiched between a plurality of scanning electrodes and a plurality of signal electrodes extending generally perpendicular to the scanning electrodes, which comprises the steps of erasing a display screen by bringing it into either a light transmitting state or a light scattering state, writing by which pixels each at a point of intersection between the scanning and signal electrodes are selectively reversed in optical state, and retaining each of the pixels in the optical state once assumed immediately after the writing step. During the erasing step, all of the pixels are applied with a high alternating voltage or a high direct current voltage.