Abstract: In a semiconductor memory having a configuration of a plurality of bits, there are provided a parity calculation circuit and a test input-output circuit, wherein the test input-output circuit is operated during a pellet checking operation, outputs the test data inputted from a test input-output terminal to data buses while being divided into a plurality of bits constituting one unit during the writing operation, and then the same test data is written into the memory cell of a plurality of bits at the specified address. During the reading operation, a parity calculation circuit performs the parity calculation with all the readout data of a plurality of bits constituting one unit to generate the parity bit and the test input-output circuit outputs the parity bit from the test input-output terminal.

Abstract: A test pattern generation circuit is stored in a semiconductor memory, a writing operation is carried out with an address sequence pattern and a test data pattern generated with a clock signal obtained from an external part during a test mode, the test data pattern and the read-out data are compared from each other during a reading-out operation, a pass or non-pass discrimination signal in the memory is attained in response to whether both of them are coincided with each other or not, the pass or non-pass discrimination signal is outputted to an external terminal, the number of test signal driving signals is reduced and the number of parallel test chips is increased so as to reduce a test cost. In addition, the memory has a power supply shut-off control circuit and a stable test is carried out by shutting-off the power supply in the case that the power supply shows a short-circuited state.