Abstract: A method of manufacturing a non-volatile semiconductor memory. The method includes forming a word gate poly layer on a substrate, wherein an upper surface of the substrate defines a plane of the substrate. The method also includes forming a first dielectric layer coupled to the word gate poly layer and patterning the word gate poly layer and the first dielectric layer to form an array of word gate structures. The method further includes forming a poly plug layer and patterning the poly plug layer to form a plurality of poly plugs surrounded in the plane of the substrate on three sides, forming a plurality of control gates, forming a second dielectric layer, planarizing the second dielectric layer using a chemical-mechanical polishing process, and depositing a metal layer to provide electrical contact to the word gate structures.

Abstract: A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.