Patents by Inventor K. Charles JANAC

K. Charles JANAC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEM AND METHOD FOR SYNTHESIS OF CONNECTIVITY TO AN INTERCONNECT IN A MULTI-PROTOCOL SYSTEM-ON-CHIP (SoC)
    Publication number: 20220263925
    Abstract: In accordance with the various aspects and embodiment of the invention, a system and method are disclosed that automate the process of generating protocol converters using machine-readable descriptions of the external hardware components interfaces and the associated protocol. One advantage of the invention is lowered mistakes in generating the protocol converters. Another advantage is increased productivity when designing the interconnect, such as a network-on-chip (NoC) interconnect used in a system-on-chip (SoC).
    Type: Application
    Filed: February 6, 2022
    Publication date: August 18, 2022
    Applicant: ARTERIS, INC.
    Inventors: K. Charles JANAC, Vincent THIBAUT, Benoit de LESCURE
  • SYSTEM AND METHOD FOR REDUCING SILICON AREA OF RESILIENT SYSTEMS USING FUNCTIONAL AND DUPLICATE LOGIC
    Publication number: 20200210544
    Abstract: A resilient system implementation in a network-on-chip with data paths being duplicated in a network translation unit.
    Type: Application
    Filed: December 29, 2018
    Publication date: July 2, 2020
    Applicant: Arteris, Inc.
    Inventor: K. Charles JANAC