Patents by Inventor K. J. Chuang

K. J. Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming separated floating gate for EEPROM application
    Patent number: 5837583
    Abstract: An EEPROM with separated floating gate to reduce the antenna ratio is disclosed. The structure of the EEPROM includes field oxides formed on a wafer. A control gate is formed in the wafer. A first gate oxide formed above the wafer for isolation. A first polysilicon portion is formed on the first gate oxide, which includes a gate for a transistor, a first contact window and a floating gate. Further, the floating gate is set above the control gate. A second gate oxide is formed on the wafer adjacent to the field oxide for isolation. A tunneling window is formed in the second gate oxide. A second polysilicon portion having a second contact window is formed on the second gate oxide. A dielectric layer is formed on the first polysilicon portion and the second polysilicon portion. Contact holes are formed in the dielectric layer and a connecting structure formed in the contact holes and on the dielectric layer for interconnection.
    Type: Grant
    Filed: November 18, 1997
    Date of Patent: November 17, 1998
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: K.-J. Chuang, H.-S. Lui
  • Separated floating gate for EEPROM application
    Patent number: 5786614
    Abstract: An EEPROM with separated floating gate to reduce the antenna ratio is disclosed. The structure of the EEPROM includes field oxides formed on a wafer. A control gate is formed in the wafer. A first gate oxide formed above the wafer for isolation. A first polysilicon portion is formed on the first gate oxide, which includes a gate for a transistor, a first contact window and a floating gate. Further, the floating gate is set above the control gate. A second gate oxide is formed on the wafer adjacent to the field oxide for isolation. A tunneling window is formed in the second gate oxide. A second polysilicon portion having a second contact window is formed on the second gate oxide. A dielectric layer is formed on the first polysilicon portion and the second polysilicon portion. Contact holes are formed in the dielectric layer and a connecting structure formed in the contact holes and on the dielectric layer for interconnection.
    Type: Grant
    Filed: April 8, 1997
    Date of Patent: July 28, 1998
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: K. J. Chuang, H. S. Lui