Abstract: Embodiments herein relate to techniques to integrate a capacitive voltage regulator in an integrated circuit (IC) package. The voltage regulator may provide a power supply to one or more load domains in the IC package. The transistors of the voltage regulator may be included on the same die as one or more of the load domains, another die, and/or an interposer of the IC package. The capacitors may be included in the same die as the transistors, in the interposer, in a package layer (e.g., package core), and/or in the same die as one or more of the load domains. Accordingly, the voltage regulator can be integrated close to the relevant load domains, delivering power with short current paths and thereby providing reduced input impedance, output impedance, and associated losses compared with prior techniques. Other embodiments may be described and claimed.

Abstract: Embodiments herein relate to a voltage regular (VR) formed from dies stacked on a package base layer. The VR can include a first part on a first die and a second part on a second die, where the different parts are selected based on characteristics of the respective die such as their voltage domains or technologies. In a capacitor-based VR, an input capacitor and switches subject to a relatively high input voltage can be provided in the first die, while a flying capacitor, output capacitor and switches subject to a relatively low output voltage can be provided in the second die. In an inductor-based VR, an inductor and one or more switches subject to a relatively high input voltage can be provided in the first die, while an output capacitor subject to a relatively low output voltage can be provided in the second die.

Abstract: Embodiments herein relate to a voltage regular (VR) formed from a first die stacked on a package base layer. The VR can have an inductor-first design in which an inductor is in the package base layer and active circuitry such as switches is in the first die. The inductor receives an input voltage, Vin, directly from the package base layer without the input voltage first entering the first die. The VR can comprise a Kappa VR which includes first and second inductors in the package base layer. The inductors can have asymmetric inductances to improve efficiency. The VR can be cascaded with a set of current multipliers or a Continuously Scalable Conversion Ratio (CSCR) capacitive regulator. Another example implementation includes a switched-inductor-capacitor converter cascaded with a set of switched capacitor current multipliers.

Abstract: Embodiments herein relate to a voltage regular (VR) formed from die stacked on a package base layer. The die can include a load die stacked on a VR die, with an intermediate layer between the two dies. The VR can include an inductor or transformer as a charge transfer component formed between the dies. For example, the inductor or transformer windings can wind around the intermediate layer and include portions of top metal layers of the VR and load die, where the load die is inverted in the stack. The intermediate layer can be magnetic or non-magnetic for an inductor, or magnetic for a transformer. The VR can optionally be divided among two dies. The VR die may have a gallium nitride substrate to handle a higher input voltage, while the load die comprises a silicon substrate.

Abstract: Embodiments herein relate to a stacked semiconductor structure which includes a first voltage regulator (VR), external to a package, for supplying current to a compute die in the package. When the required current exceeds a threshold, an additional current source is activated. The additional current source can include a second VR, also external to the package, for supplying current to an integrated voltage regulator (IVR) in the package. The IVR performs voltage down conversion and current multiplication to output a portion of the required current above the threshold, while the output of the first VR is capped at the threshold.

Abstract: A computational current sensor, that enhances traditional Kalman filter based current observer techniques, with transient tracking enhancements and an online parasitic parameter identification that enhances overall accuracy during steady state and transient events while guaranteeing convergence. During transient operation (e.g., a voltage droop), a main filter is bypassed with estimated values calculated from a charge balance principle to enhance accuracy while tracking transient current surges of the DC-DC converter. To address the issue of dependency on a precise model parameter information and further improve accuracy, an online identification algorithm is included to track the equivalent parasitic resistance at run-time.

Abstract: Embodiments herein relate to a voltage regular (VR) formed by components which are distributed over a stack of dice or wafers. Separate VRs can be provided in separate dice or wafers, where their outputs are coupled at an output path. A common control circuit can be used to control each VR. Passive components of a VR can be distributed on separate dice. For example, capacitors or inductors on the different dice or wafers can be coupled in parallel or in series, respectively. The stack can include dice or wafers of different types, such as silicon and Gallium Nitride. A first VR on a first type of die or wafer can be arranged in cascade with a second VR on a second type of die or wafer. The components in the different dice or wafers can be coupled by vias such as through-silicon vias.

Abstract: Embodiments herein relate to a multi-bit flip-flop circuit which uses unidirectional transistors to allow sharing of transistors among a set of flip-flops, while avoiding charge sharing within or between the flip-flops. Clock devices in the circuit can be shared to reduce the clock transistor gate capacitance and associated power consumption. The shared transistors can provide keeper circuits and/or tri-state inverters in a primary latch and a secondary latch in each flip-flop. One example implementation uses tri-state keeper sharing. Another example implementation uses tri-state keeper and/or pass gate sharing. Another example implementation uses pass gate sharing and no keeper.

Abstract: Various embodiments herein provide a switched capacitor voltage converter with a subset of one or more phases that selectively provide a decoupling capacitance. The voltage converter may include multiple phases coupled in parallel between an input terminal and an output terminal. The individual phases may include a capacitor and a set of switches. A first subset of one or more of the phases may operate in a switching mode in which the respective set of switches open and close to generate an output voltage at the output terminal based on an input voltage at the input terminal. The voltage converter may further include a second subset of one or more phases that are selectively operable in the switching mode or in a decoupling mode. In the decoupling mode, the switches of the respective phase may maintain the capacitor coupled between the output terminal and ground. Other embodiments may be described and claimed.

Abstract: Embodiments herein relate to a pulse generator which provides first and second clock pulses to one or more pulsed latches, where the pulse generator replicates a delay of the pulsed latches in providing the first and second clock pulses. The pulse generator can include a replica of latch components in the pulsed latches such as a tri-state inverter, a transmission gate and inverters, where an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter, and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter can be a modified tri-state inverter with an output forced to “1” when a clock signal is “0.” In one approach, the latch components of the pulse generator are to write a logic 1 when a clock signal goes high.

Abstract: A fused dot-product multiply-accumulate (MAC) circuit may support variable precisions of floating-point data elements to perform computations (e.g., MAC operations) in deep learning operations. An operation mode of the circuit may be selected based on the precision of an input element. The operation mode may be a FP16 mode or a FP8 mode. In the FP8 mode, product exponents may be computed based on exponents of floating-point input elements. A maximum exponent may be selected from the one or more product exponents. A global maximum exponent may be selected from a plurality of maximum exponents. A product mantissa may be computed and aligned with another product mantissa based on a difference between the global maximum exponent and a corresponding maximum exponent. An adder tree may accumulate the aligned product mantissas and compute a partial sum mantissa. The partial sum mantissa may be normalized using the global maximum exponent.

Abstract: Embodiments herein relate to a current sensor for a power converter such as a buck converter. The power converter is fabricated on a high bandgap semiconductor die while the current sensor includes a portion on the same die and a portion on a silicon die. The portion on the same die includes a sense transistor, while the portion on the silicon die includes a feedback circuit for controlling a voltage of the sense transistor to ensure it is biased according to the bias of a switching transistor of the power converter. A current of the sense transistor can then be processed such as by an averaging or sampling process.

Abstract: An apparatus, system, and method for digital voltage regulator (DVR) control are provided. A DVR includes comparators configured to determine whether VLOAD drops below a gradual non-linear control (NLC) undershoot threshold voltage, rises above or drops below a reference voltage, and rises above a gradual NLC overshoot threshold voltage, respectively, power gates (PGs) configured to adjust VOUT based on a provided PG code; and VR controller circuitry comprising synchronous LC circuitry configured to increase or decrease, by a first increment, the PG code responsive to the VLOAD dropping below the reference voltage and rising above the reference voltage, and asynchronous gradual NLC circuitry configured to increase or decrease, by a second increment greater than the first increment and less than half a maximum PG code value, the PG code responsive to the VLOAD dropping below the gradual NLC undershoot threshold voltage and rising above the gradual NLC overshoot threshold voltage.

Abstract: An apparatus, system, and method for voltage regulator (VR) control are provided. An apparatus can include first, second, and third comparators configured to determine whether a load voltage (VLOAD) drops below a lower non-linear control (NLC) threshold, drops below a lower linear control (LC) threshold, and exceeds an upper LC threshold, respectively. The apparatus can include power gates (PGs) configured to adjust an output voltage (VOUT) based on a provided power gate (PG) code. The apparatus can include voltage regulator (VR) controller circuitry comprising synchronous LC circuitry and asynchronous NLC circuitry, the LC circuitry configured to increment or decrement the PG code responsive to the VLOAD dropping below the LC threshold and exceeding the upper LC threshold, respectively, and the NLC circuitry configured to increase the PG code based on a number of consecutive NLC droop events and responsive to the VLOAD dropping below the lower NLC threshold.

Abstract: A computational current sensor, that enhances traditional Kalman filter based current observer techniques, with transient tracking enhancements and an online parasitic parameter identification that enhances overall accuracy during steady state and transient events while guaranteeing convergence. During transient operation (e.g., a voltage droop), a main filter is bypassed with estimated values calculated from a charge balance principle to enhance accuracy while tracking transient current surges of the DC-DC converter. To address the issue of dependency on a precise model parameter information and further improve accuracy, an online identification algorithm is included to track the equivalent parasitic resistance at run-time.

Abstract: A FPMAC operation has two operands: an input operand and a weight operand. The operands may have a format of FP16, BF16, or INT8. Each operand is split into two portions. The two portions are stored in separate storage units. Then operands are transferred to register files of a PE, with each register file storing bits of an operand sequentially. The PE performs the FPMAC operation based on the operands. The PE may include an FPMAC unit configured to compute an individual partial sum of the PE. The PE may also include an FP adder to accumulate the individual partial sum with other data, such as an output from another PE or an output form another PE array. The FP adder may be fused with the FPMAC unit in a single circuit that can do speculative alignment and has separate critical paths for alignment and normalization.

Abstract: In one embodiment, a processor comprises a first neuro-synaptic core comprising first circuitry to configure the first neuro-synaptic core as a neuron core responsive to a first value specified by a configuration parameter; and configure the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter.

Abstract: Apparatus and method for a scalable, free running neuromorphic processor. For example, one embodiment of a neuromorphic processing apparatus comprises: a plurality of neurons; an interconnection network to communicatively couple at least a subset of the plurality of neurons; a spike controller to stochastically generate a trigger signal, the trigger signal to cause a selected neuron to perform a thresholding operation to determine whether to issue a spike signal.

Abstract: In one embodiment, a method comprises receiving a selection of a neural network topology type; identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme.

Abstract: In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.