Abstract: An improved NAND-type memory cell structure having improved reliability and endurance. Since a high risk area for oxide breakdown and/or current leakage exists in the tunnel oxide layer, source/drain overlap region, the present invention provides a NAND-type memory cell fabricated using controlled formation of the tunnel oxide layer.

Abstract: A single tunnel gate oxidation process for fabricating NAND memory strings where the gate oxide of the select transistors and the floating gate memory transistors are fabricated in a single oxidation step is disclosed. The select gate transistors and the floating gate memory transistors have an oxide thickness of 85 Å-105 Å. For single tunnel gate approach, a careful selection of the medium doped source/drain region implant conditions is necessary for proper function of the NAND memory string. In one embodiment, the medium doped source/drain region is doped with Arsenic to a concentrations of 1013-1014/cm2.

Abstract: A voltage control circuit that narrows the distribution of threshold voltages of memory cells by using nonlinearly incremented programming voltages. To do so, the voltage control circuit applies to the memory cells a first program pulse of a first voltage, a second program pulse of a second voltage to the memory cell, and a third program pulse of a third voltage, where the difference between the third voltage and the second voltage is less than the difference between the second voltage and the first voltage.

Abstract: A programming and erase method that extends erase time degradation of nonvolatile memory devices by using a constant erase voltage and a set of program voltages, where the average program voltage of the set of the program voltages is approximately equal to the constant erase voltage.