Abstract: Eyewear including a multi-layered display having an adhesive bonding the layers together at an offset distance inward from an outer edge of the layers. The display has an image display layer, such as an optical waveguide in one example, and a pair of layers encompassing the image display layer and which may comprise optically transparent substrates, such as glass. A respective adhesive is positioned the offset distance inward from the outer edge of the display layer between the image display layer and each of the pair of layers to reduce stress in the display. Each of the adhesives may be a continuous bead such that there is no adhesive between the pair of layers and the image display layer at the outer edges. In one example, the offset distance may be at least double the thickness of the image display layer to reduce stress in the image display layer.

Abstract: Eyewear including a multi-layered display having an adhesive bonding the layers together at an offset distance inward from an outer edge of the layers. The display has an image display layer, such as an optical waveguide in one example, and a pair of layers encompassing the image display layer and which may comprise optically transparent substrates, such as glass. A respective adhesive is positioned the offset distance inward from the outer edge of the display layer between the image display layer and each of the pair of layers to reduce stress in the display. Each of the adhesives may be a continuous bead such that there is no adhesive between the pair of layers and the image display layer at the outer edges. In one example, the offset distance may be at least double the thickness of the image display layer to reduce stress in the image display layer.

Abstract: Eyewear including a multi-layered display having an adhesive bonding the layers together at an offset distance inward from an outer edge of the layers. The display has an image display layer, such as an optical waveguide in one example, and a pair of layers encompassing the image display layer and which may comprise optically transparent substrates, such as glass. A respective adhesive is positioned the offset distance inward from the outer edge of the display layer between the image display layer and each of the pair of layers to reduce stress in the display. Each of the adhesives may be a continuous bead such that there is no adhesive between the pair of layers and the image display layer at the outer edges. In one example, the offset distance may be at least double the thickness of the image display layer to reduce stress in the image display layer.

Abstract: Eyewear including a multi-layered display having an adhesive bonding the layers together at an offset distance inward from an outer edge of the layers. The display has an image display layer, such as an optical waveguide in one example, and a pair of layers encompassing the image display layer and which may comprise optically transparent substrates, such as glass. A respective adhesive is positioned the offset distance inward from the outer edge of the display layer between the image display layer and each of the pair of layers to reduce stress in the display. Each of the adhesives may be a continuous bead such that there is no adhesive between the pair of layers and the image display layer at the outer edges. In one example, the offset distance may be at least double the thickness of the image display layer to reduce stress in the image display layer.

Abstract: Cutting a wafer having devices, such as glass optical waveguides, into die by cutting into both sides of the wafer to reduce or eliminate micro-cracks and defects in the die. The wafer can be cut by simultaneously cutting the wafer from both sides using separate lasers at a controlled depth. The wafer can also be sequentially cut by cutting into one side of the wafer, flipping the wafer, and then cutting into the other side of the wafer. A processor controls the power of each laser to select the depth of each cut, such that each cut may be 50% into the wafer, or other depths such as 30% for one cut and 70% for the other cut. The wafer may be cut into the bottom surface of the wafer first, and then cut into the top surface of the wafer having the optical waveguides.

Abstract: The present invention relates to purine compounds that are useful as kinase inhibitors. More particularly, the present invention relates to purine compounds, methods for their preparation, pharmaceutical compositions containing these compounds and uses of these compounds in the treatment of proliferative conditions or disorders. These compounds may be useful as medicaments for the treatment of a number of proliferative conditions or disorders including tumors and cancers as well as other disorders or conditions related to or associated with PI3 and/or mTOR kinases.

Abstract: The present invention relates to purine compounds that are useful as kinase inhibitors. More particularly, the present invention relates to purine compounds, methods for their preparation, pharmaceutical compositions containing these compounds and uses of these compounds in the treatment of proliferative conditions or disorders. These compounds may be useful as medicaments for the treatment of a number of proliferative conditions or disorders including tumours and cancers as well as other disorders or conditions related to or associated with PI3 and/or mTOR kinases.

Abstract: The present invention relates to purine compounds that are useful as kinase inhibitors. More particularly, the present invention relates to purine compounds, methods for their preparation, pharmaceutical compositions containing these compounds and uses of these compounds in the treatment of proliferative conditions or disorders. These compounds may be useful as medicaments for the treatment of a number of proliferative conditions or disorders including tumors and cancers as well as other disorders or conditions related to or associated with PI3 and/or mTOR kinases.

Abstract: A new self calibration technique for pipe line A/D converters is presented. It consists of calibration by correcting the reference voltage to each stage by means of a tunable MOSFET attenuator. This simplifies the calibration circuit in each stage and shifts most of the calibration task to a hardware that is shared by all the stages.

Abstract: In order to test the functional and parametric characteristics of a unit without overloading a host computer, the host computer downloads a testing program to a plurality of digital signal processor modules which do all of the functional environmental emulation data generation and analysis of the data received from the unit under test. A reconfigurable application interface module is also programmed at the same time as the digital signal processor modules and is thus configured to accept basic emulation data generated by the digital signal processor modules and convert those data to the data environment that the unit under test is expected to experience in use. The application interface module also converts the data received from the unit under test into a format that the digital signal processor modules can analyze, the results of which analysis are made available to the host computer.

Abstract: A semiconductor chip (26) is attached to a leadframe (20, 30, 40). The leadframe (20, 30, 40) has an opening (24) or a cavity (34, 44) for receiving the semiconductor chip (26). The opening (24) or the cavity (34, 44) and the semiconductor chip (26) have corresponding shapes. The opening (24) or the cavity (34, 44) is made such that they are smaller than the size of the semiconductor chip (26) at room temperature. The opening (24) or the cavity (34, 44) is expanded and the semiconductor chip (26) is placed in the opening (24) or the cavity (34, 44). Subsequent to placing the semiconductor chip (26) in the opening (24) or the cavity (34, 44), the leadframe (20, 30, 40) is cooled so that an edge (25) of the leadframe grips a corresponding edge (29) of the semiconductor chip (26).

Abstract: A plastic package (10) with a heat sink (11, 27, 28, 32) has a stress relief wall (18, 21, 33) formed on its upper surface. A semiconductor die (12) is mounted on the heat sink (11, 27, 28, 32) such that the top of a semiconductor die (12) is below the level of the top of the wall (18, 21, 33), and the wall (18, 21, 33) absorbs stresses which otherwise would be applied to the semiconductor die (12). The package (10) is simple to fabricate and assemble, and provides a mold lock (23, 24, 31) which serves to hold the plastic material (13) tightly to the heat sink (11, 27, 28, 32). Extra die bond material (26) can be used to increase heat flow without compromising other characteristics of the package (10).