Patents by Inventor K. Sridharan
K. Sridharan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126457Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.Type: ApplicationFiled: December 11, 2023Publication date: April 18, 2024Inventors: Rohit Natarajan, Jurgen M. Schulz, Christopher D. Shuler, Rohit K. Gupta, Thomas T. Zou, Srinivasa Rangan Sridharan
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Publication number: 20240004750Abstract: An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). The first partition includes a host processor that executes an exception handler for managing reported errors. A message converter unit of the second partition assists in generating messages based on detected errors in the second partition. The message converter unit receives requests from hardware components of the second partition for handling errors and translates MCA addresses between the first partition and the second partition. To support the message converter unit, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor, and the host processor sends address translation information.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Vilas K. Sridharan, Magiting Talisayon, Srikanth Masanam, Dean A. Liberty
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Publication number: 20240004744Abstract: An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). When a host processor in the first partition detects an error that requires information from processor cores of the second partition, the host processor generates an access request with a target address pointing to a storage location in a memory of the second partition, not the first partition. When the host processor receives the requested error log information from the second partition, the host processor completes processing of the error. To support the host processor in generating the target address for the access request, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Vilas K. Sridharan, Dean A. Liberty, Magiting Talisayon, Srikanth Masanam
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Patent number: 11657004Abstract: A method and system for memory attack mitigation in a memory device includes receiving, at a memory controller, an allocation of a page in memory. One or more device controllers detects an aggressor-victim set within the memory. Based upon the detection, an address of the allocated page is identified for further action.Type: GrantFiled: December 17, 2020Date of Patent: May 23, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Sudhanva Gurumurthi, Vilas K. Sridharan
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Publication number: 20220197827Abstract: A method and system for memory attack mitigation in a memory device includes receiving, at a memory controller, an allocation of a page in memory. One or more device controllers detects an aggressor-victim set within the memory. Based upon the detection, an address of the allocated page is identified for further action.Type: ApplicationFiled: December 17, 2020Publication date: June 23, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Sudhanva Gurumurthi, Vilas K. Sridharan
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Publication number: 20210342241Abstract: A method and apparatus for predicting and managing a device failure includes responsive to a predicted failure of a memory device, the predicted failure based on sensor data associated with the memory device, determining a further action for the memory device.Type: ApplicationFiled: April 29, 2020Publication date: November 4, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Sudhanva Gurumurthi, Vilas K. Sridharan
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Patent number: 11061753Abstract: Systems, apparatuses, and methods for implementing a hardware enforcement mechanism to enable platform-specific firmware visibility into an error state ahead of the operating system are disclosed. A system includes at least one or more processor cores, control logic, a plurality of registers, platform-specific firmware, and an operating system (OS). The control logic allows the platform-specific firmware to decide if and when the error state is visible to the OS. In some cases, the platform-specific firmware blocks the OS from accessing the error state. In other cases, the platform-specific firmware allows the OS to access the error state such as when the OS needs to unmap a page. The control logic enables the platform-specific firmware, rather than the OS, to make decisions about the replacement of faulty components in the system.Type: GrantFiled: March 29, 2018Date of Patent: July 13, 2021Assignee: Advanced Micro Devices, Inc.Inventors: Dean A. Liberty, Vilas K. Sridharan, Michael T. Clark, Jelena Ilic, David S. Christie, James R. Williamson, Cristian Constantinescu
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Publication number: 20210182135Abstract: A method and apparatus for predicting and managing a fault in memory includes detecting an error in data. The error is compared to one or more stored errors in a filter, and based upon the comparison, the error is predicted as a transient error or a permanent error for further action.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Sudhanva Gurumurthi, Vilas K. Sridharan
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Patent number: 10572839Abstract: Various examples are directed to systems and methods for aggregating user tool experience. A record ingestion circuit may receive action record data from a user tool that describes an action performed with the user tool by the user. The record ingestion circuit may also receive user name data describing the user. A record analytics circuit may generate user experience data for the user describing a plurality of actions performed by the user with the user tool. An application programming interface (API) circuit may receive from a requesting application a query for data describing the plurality of actions and send to the requesting application the data describing the plurality of actions.Type: GrantFiled: July 1, 2016Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Bradford H. Needham, David A. Sandage, K. Sridharan, Bernard N. Keany
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Publication number: 20190303230Abstract: Systems, apparatuses, and methods for implementing a hardware enforcement mechanism to enable platform-specific firmware visibility into an error state ahead of the operating system are disclosed. A system includes at least one or more processor cores, control logic, a plurality of registers, platform-specific firmware, and an operating system (OS). The control logic allows the platform-specific firmware to decide if and when the error state is visible to the OS. In some cases, the platform-specific firmware blocks the OS from accessing the error state. In other cases, the platform-specific firmware allows the OS to access the error state such as when the OS needs to unmap a page. The control logic enables the platform-specific firmware, rather than the OS, to make decisions about the replacement of faulty components in the system.Type: ApplicationFiled: March 29, 2018Publication date: October 3, 2019Inventors: Dean A. Liberty, Vilas K. Sridharan, Michael T. Clark, Jelena Ilic, David S. Christie, James R. Williamson, Cristian Constantinescu
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Patent number: 10191657Abstract: The disclosed embodiments provide a system for detecting and managing memory inefficiency in a software program. During operation, the system obtains a first snapshot of a heap for a software program, wherein the first snapshot includes a first set of objects stored in the heap at a first time. Next, the system applies a compression technique to the first snapshot to obtain a first set of inefficiency metrics for the first set of objects, wherein each inefficiency metric in the first set of inefficiency metrics represents a memory inefficiency of an object in the heap at the first time. The system then outputs the first set of inefficiency metrics with additional attributes of the first set of objects to improve identification of the memory inefficiency in the software program.Type: GrantFiled: December 15, 2015Date of Patent: January 29, 2019Assignee: Microsoft Technology Licensing, LLCInventors: John W. Nicol, Cuong H. Tran, Haricharan K. Ramachandra, Badrinath K. Sridharan
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Patent number: 10019340Abstract: A system, apparatus, and methods are provided for managing on-demand profiling of one or more instances of a software application executing on a plurality of machines within one or more data centers. During operation, the system executes the one or more instances of the software application on the plurality of machines. Next, the system publishes, to a command channel, a command message that comprises a profiling request, wherein the profiling request specifies a subset of the machines. The system then receives, via a data channel, one or more data messages from the subset of the machines, wherein the data messages comprise data gathered by the subset of the machines in response to receiving the command message. Next, the system then evaluates the performance of the software application by aggregating and processing the data messages. Responsive to detecting an anomaly in the performance, the system then executes one or more remedies.Type: GrantFiled: March 21, 2016Date of Patent: July 10, 2018Assignee: Microsoft Technology Licensing, LLCInventors: John W. Nicol, Zhenyun Zhuang, Arman H. Boehm, Tao Feng, Haricharan K. Ramachandra, Badrinath K. Sridharan
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Patent number: 9952787Abstract: The disclosed embodiments provide a system for detecting and managing inefficiency in external services. During operation, the system obtains a snapshot of a data stream transmitted over an external service from a computer system at a first time. Next, the system applies a compression technique to the snapshot to obtain a set of inefficiency metrics for a set of data elements in the snapshot. The system then outputs the set of inefficiency metrics with additional attributes of the data stream to improve identification of inefficiency in the data stream.Type: GrantFiled: May 20, 2016Date of Patent: April 24, 2018Assignee: Microsoft Technology Licensing, LLCInventors: John W. Nicol, Ritesh Maheshwari, Nicholas P. Baggott, Haricharan K. Ramachandra, Badrinath K. Sridharan
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Patent number: 9952772Abstract: The disclosed embodiments provide a system for detecting and managing inefficiency in local storage. During operation, the system obtains a first snapshot of data in local storage of a computer system, wherein the first snapshot comprises a first set of data elements in the local storage at a first time. Next, the system applies a compression technique to the first snapshot to obtain a first set of inefficiency metrics for the first set of data elements. The system then outputs the first set of inefficiency metrics with additional attributes of the data to improve management of inefficiency in the data.Type: GrantFiled: May 20, 2016Date of Patent: April 24, 2018Assignee: Microsoft Technology Licensing, LLCInventors: John W. Nicol, Ritesh Maheshwari, Nicholas P. Baggott, Haricharan K. Ramachandra, Badrinath K. Sridharan
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Patent number: 9886195Abstract: The disclosed embodiments provide a system for analyzing data from a monitored system. During operation, the system identifies a difference between a performance of an application and a service-level agreement (SLA) of the application. Next, the system determines a correlation between the performance of the application and a disk input/output (I/O) performance of a data storage device used by the application. When the correlation exceeds a threshold, the system outputs a recommendation to migrate the application between the data storage device and a different type of data storage device.Type: GrantFiled: January 14, 2016Date of Patent: February 6, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Zhenyun Zhuang, Sergiy Zhuk, Haricharan K. Ramachandra, Badrinath K. Sridharan
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Publication number: 20180005154Abstract: Various examples are directed to systems and methods for aggregating user tool experience. A record ingestion circuit may receive action record data from a user tool that describes an action performed with the user tool by the user. The record ingestion circuit may also receive user name data describing the user. A record analytics circuit may generate user experience data for the user describing a plurality of actions performed by the user with the user tool. An application programming interface (API) circuit may receive from a requesting application a query for data describing the plurality of actions and send to the requesting application the data describing the plurality of actions.Type: ApplicationFiled: July 1, 2016Publication date: January 4, 2018Inventors: Bradford H. Needham, David A. Sandage, K. Sridharan, Bernard N. Keany
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Patent number: 9852041Abstract: Techniques for categorizing exceptions and logs are described. For example, exception data of an exception that occurred on a machine is accessed. The exception data includes a stack trace of the exception. A determination is made that the exception is unique based on the stack track of the exception. Responsive to the determination that the exception is unique, the exception is categorized, by a machine including a memory and at least one processor, into one or more categories based on the stack trace of the exception.Type: GrantFiled: September 30, 2013Date of Patent: December 26, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Nicholas Baggott, Badrinath K. Sridharan, Toon Sripatanaskul
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Publication number: 20170336995Abstract: The disclosed embodiments provide a system for detecting and managing inefficiency in external services. During operation, the system obtains a snapshot of a data stream transmitted over an external service from a computer system at a first time. Next, the system applies a compression technique to the snapshot to obtain a set of inefficiency metrics for a set of data elements in the snapshot. The system then outputs the set of inefficiency metrics with additional attributes of the data stream to improve identification of inefficiency in the data stream.Type: ApplicationFiled: May 20, 2016Publication date: November 23, 2017Applicant: LinkedIn CorporationInventors: John W. Nicol, Ritesh Maheshwari, Nicholas P. Baggott, Haricharan K. Ramachandra, Badrinath K. Sridharan
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Publication number: 20170336984Abstract: The disclosed embodiments provide a system for detecting and managing inefficiency in local storage. During operation, the system obtains a first snapshot of data in local storage of a computer system, wherein the first snapshot comprises a first set of data elements in the local storage at a first time. Next, the system applies a compression technique to the first snapshot to obtain a first set of inefficiency metrics for the first set of data elements. The system then outputs the first set of inefficiency metrics with additional attributes of the data to improve management of inefficiency in the data.Type: ApplicationFiled: May 20, 2016Publication date: November 23, 2017Applicant: LinkedIn CorporationInventors: John W. Nicol, Ritesh Maheshwari, Nicholas P. Baggott, Haricharan K. Ramachandra, Badrinath K. Sridharan
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Patent number: 9823875Abstract: A system, method, and apparatus are provided for performing a transparent hybrid data storage scheme in which data are stored as blocks distributed among one or more flash-based storage devices (e.g., solid state drives) and one or more magnetic storage devices (e.g., magnetic disk drives). Files larger than a given size (e.g., 1 MB) are segmented into blocks of that size and stored on one or more devices; blocks of one file may be stored on devices of different types. Periodically, a utility function calculates utility values for each of some or all stored blocks based on frequency of access to the block, frequency of access of a particular type (e.g., random, sequential), a preference regarding where to store the block or the corresponding file, and/or other factors. Blocks having the highest utility values are subject to migration between devices of different types and/or the same type (e.g., for load-balancing).Type: GrantFiled: August 31, 2015Date of Patent: November 21, 2017Assignee: LinkedIn CoporationInventors: Zhenyun Zhuang, Sergiy Zhuk, Haricharan K. Ramachandra, Cuong H. Tran, Badrinath K. Sridharan