Abstract: A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress.

Abstract: A porous diamond dielectric material having a low dielectric constant and a method of forming such a material are described herein. A porous diamond dielectric material demonstrates high mechanical strength and has a low dielectric constant because of the presence of the pores. The dielectric constant is further decreased by the conversion of the sp2 type carbon bond terminations of the interior surface of the pores to sp3 type carbon bond terminations. This is accomplished by hydrogenation of the porous diamond dielectric material.

Abstract: A layer of reduced stress is formed on a substrate using an HDP-CVD system by delaying or interrupting the application of capacitively coupled RF energy. The layer is formed by introducing a process gas into the HDP system chamber and forming a plasma from the process gas by the application of RF power to an inductive coil. After a selected period, a second layer of the film is deposited by maintaining the inductively-coupled plasma and biasing the plasma toward the substrate to enhance the sputtering effect of the plasma. In a preferred embodiment, the deposited film is a silicon oxide film, and biasing is performed by application of capacitively coupled RF power from RF generators to a ceiling plate electrode and wafer support electrode.

Abstract: Electronic apparatus having a heat transfer/stress-reducing layer combined with a device layer and methods of fabricating such electronic apparatus provide a means for incorporating a heat transfer layer in an integrated circuit. A structure with a diamond layer incorporated beneath a device layer provides a heat transfer layer for the structure. In an embodiment, a compliant layer is formed between a diamond layer and a substrate to provide stress reduction. In another embodiment, a diamond layer is formed as a layer of islands of diamond from nucleation centers to provide stress reduction.

Abstract: A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress.

Abstract: A diamond insulator collar and methods for fabricating a diamond insulator collar for electrical discharge gas plasma EUV source. The insulating collar is positioned at the base of the central electrode in the pre-ionization region of the plasma head. The insulating collar prevents electrical shorting between the outer electrode and the central electrode in this region. In one embodiment of a method for providing a wire mesh-reinforced diamond insulator collar, a mandrel is provided that replicates the shape of the base of the central electrode. A wire mesh is wrapped around the mandrel conforming to the shape of the mandrel. The wire mesh is coated with electrically insulating diamond using known plasma enhanced chemical vapor deposition (CVD) techniques to form a non-porous coating. The mandrel is removed from the diamond-coated wire mesh providing a porous-free wire-reinforced diamond insulator collar. Embodiments of non-wire reinforced collars are presented.

Abstract: Erosion-resistive coatings are provided on critical plasma-facing surfaces of an electrical gas plasma head for an EUV source. The erosion-resistive coatings comprise diamond and diamond-like materials deposited onto the critical plasma-facing surfaces. A pure diamond coating is deposited onto the plasma exposed insulator surfaces using, for example, a chemical vapor deposition processes. The diamond coating is made conductive by selective doping with p-type material, such as, but not limited to, boron and graphite.

Abstract: Damage-resistant coatings are provided on radiation-exposed surfaces of EUV lithographic components. The diamond coating provides resistance to particle impingement, cleaning processes, and degradation due to high temperatures. The diamond coating is beneficial when deposited on the reflecting surface of an EUV Si/Mo multilayer mirror, the reflecting surface of an EUV Si/Mo multilayer reflective mask, and radiation-exposed surfaces of EUV debris shield. The diamond coating provides longer lasting EUV components.

Abstract: A layer of reduced stress is formed on a substrate using an HDP-CVD system by delaying or interrupting the application of capacitively coupled RF energy. The layer is formed by introducing a process gas into the HDP system chamber and forming a plasma from the process gas by the application of RF power to an inductive coil. After a selected period, a second layer of the film is deposited by maintaining the inductively-coupled plasma and biasing the plasma toward the substrate to enhance the sputtering effect of the plasma. In a preferred embodiment, the deposited film is a silicon oxide film, and biasing is performed by application of capacitively coupled RF power from RF generators to a ceiling plate electrode and wafer support electrode.

Abstract: Disclosed are solar cells employing slightly curved or nearly flat monocrystalline silicon ribbons. The ribbons are formed by cutting or slicing monocrystalline hollow tubes along their lengths, the tubes having been formed according to crystal growing processes disclosed in U.S. Pat. No. 3,591,348.