Patents by Inventor Ka Kei Kwok
Ka Kei Kwok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9483594Abstract: This application discloses an electronic design automation tool configured to perform one or more static reset checks on reset functionality in a circuit design. The electronic design automation tool can detect the reset functionality in the circuit design, identify a portion of the circuit design having a set of resettable components, and determine whether the portion of the circuit design includes a reset design error based, at least in part, on the reset functionality in the circuit design. The static reset checks can include a domain congruency check, a reset skew check, and a glitch detection check, each of which can identify different design errors that may cause reset functionality in the circuit design to operate improperly.Type: GrantFiled: September 3, 2014Date of Patent: November 1, 2016Assignee: Mentor Graphics CorporationInventors: Ka-kei Kwok, Ping Yeung, Priya Viswanathan
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Publication number: 20160063161Abstract: This application discloses an electronic design automation tool configured to perform one or more static reset checks on reset functionality in a circuit design. The electronic design automation tool can detect the reset functionality in the circuit design, identify a portion of the circuit design having a set of resettable components, and determine whether the portion of the circuit design includes a reset design error based, at least in part, on the reset functionality in the circuit design. The static reset checks can include a domain congruency check, a reset skew check, and a glitch detection check, each of which can identify different design errors that may cause reset functionality in the circuit design to operate improperly.Type: ApplicationFiled: September 3, 2014Publication date: March 3, 2016Inventors: Ka-kei Kwok, Ping Yeung, Priya Viswanathan
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Patent number: 9117044Abstract: The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation.Type: GrantFiled: July 15, 2014Date of Patent: August 25, 2015Assignee: Mentor Graphics CorporationInventors: Ka-Kei Kwok, Priya Viswanathan, Rojer Raji Sabbagh, Ramesh Sathianathan
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Publication number: 20150026654Abstract: The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation.Type: ApplicationFiled: July 15, 2014Publication date: January 22, 2015Inventors: Ka-Kei Kwok, Priya Viswanathan, Rojer Raji Sabbagh, Ramesh Sathianathan
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Patent number: 8914761Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: GrantFiled: May 6, 2013Date of Patent: December 16, 2014Assignee: Mentor Graphics CorporationInventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, Jr.
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Patent number: 8819599Abstract: The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation.Type: GrantFiled: November 9, 2009Date of Patent: August 26, 2014Assignee: Mentor Graphics CorporationInventors: Ka-Kei Kwok, Priya Viswanathan, Rojer Raji Sabbagh, Ramesh Sathianathan
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Publication number: 20130246985Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Applicant: Mentor Graphics CorporationInventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, JR.
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Patent number: 8438516Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: GrantFiled: May 4, 2010Date of Patent: May 7, 2013Assignee: Mentor Graphics CorporationInventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, Jr.
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Patent number: 8271918Abstract: Methods and apparatus for performing automated formal clock domain crossing verification on a device are detailed. In various implementations of the invention, a device may be analyzed, wherein the clock domain crossing boundaries are identified. Subsequently, a formal clock domain crossing verification method may be applied to the identified clock domain crossing boundaries, resulting in clock domain crossing assertions being identified. After which the identified assertions may be promoted for post clock domain crossing analysis. With various implementations of the invention, a formal clock domain crossing method is provided, wherein the device components near an identified clock domain crossing are extracted. Assertions may then be synthesized and verified based upon the extracted components. Various implementations of the invention provide for clock domain crossing verification to be performed iteratively, wherein a larger and larger selection of the device is extracted during formal verification.Type: GrantFiled: September 14, 2009Date of Patent: September 18, 2012Assignee: Mentor Graphics CorporationInventors: Ka-Kei Kwok, Bing Li, Tai An Ly, Rojer Raji Sabbagh
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Publication number: 20100287524Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: ApplicationFiled: May 4, 2010Publication date: November 11, 2010Inventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, JR.
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Publication number: 20100242003Abstract: The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation.Type: ApplicationFiled: November 9, 2009Publication date: September 23, 2010Inventor: Ka-Kei Kwok
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Publication number: 20100199244Abstract: Methods and apparatus for performing automated formal clock domain crossing verification on a device are detailed. In various implementations of the invention, a device may be analyzed, wherein the clock domain crossing boundaries are identified. Subsequently, a formal clock domain crossing verification method may be applied to the identified clock domain crossing boundaries, resulting in clock domain crossing assertions being identified. After which the identified assertions may be promoted for post clock domain crossing analysis. With various implementations of the invention, a formal clock domain crossing method is provided, wherein the device components near an identified clock domain crossing are extracted. Assertions may then be synthesized and verified based upon the extracted components. Various implementations of the invention provide for clock domain crossing verification to be performed iteratively, wherein a larger and larger selection of the device is extracted during formal verification.Type: ApplicationFiled: September 14, 2009Publication date: August 5, 2010Inventors: Ka-Kei Kwok, Bing Li, Tai An Ly, Rojer Raji Sabbagh
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Patent number: 7454728Abstract: During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.Type: GrantFiled: June 7, 2007Date of Patent: November 18, 2008Inventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Ross Andrew Andersen, Ping Fai Yeung, Neil Patrick Hand, Lawrence Curtis Widdoes, Jr.
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Patent number: 7356789Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: GrantFiled: May 27, 2005Date of Patent: April 8, 2008Inventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, Jr.
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Patent number: 7243322Abstract: During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.Type: GrantFiled: June 1, 2004Date of Patent: July 10, 2007Inventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Ross Andrew Ander, Ping Fai Yeung, Neil Patrick Hand, Lawrence Curtis Widdoes, Jr.