Abstract: A transistor panel used for active matrix display devices includes islands of single crystal silicon formed on a transparent quartz substrate and arranged in rows and columns, with an NMOS transistor formed in each island. Each transistor includes source, drain and channel regions and an isolated pixel reference voltage region. A silicon body tie connects the channel region to the pixel reference voltage region and acts as a current sink for unwanted carriers thereby greatly increasing the snapback voltage. A metallization extends to each transistor and is in contact with each reference voltage region to form a body tie buss. The portion of the body tie that overlaps the pixel electrode may be sized to provide a storage capacitor for improved display performance. The unique body tie design obviates the need for a separate light shield layer, provides a dramatically increased aperture ratio and is compatible with normal high temperature silicon processes.