Patents by Inventor Ka Wa CHEUNG

Ka Wa CHEUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170365489
    Abstract: A method of fabricating a receptacle down BGA carrier having a top surface and a bottom surface, the method comprising combining a conductive portion and a molded dielectric portion, said dielectric portion having an inner surface intersecting said top surface, said inner surface forming a cavity for receiving a die; selectively etching part of said conductive portion; and applying solder resist to a portion of a top surface of said conductive portion.
    Type: Application
    Filed: September 6, 2017
    Publication date: December 21, 2017
    Inventor: Ka Wa CHEUNG
  • Patent number: 9786518
    Abstract: A method of fabricating a receptacle down BGA carrier having a top surface and a bottom surface, the method comprising combining a conductive portion and a molded dielectric portion, said dielectric portion having an inner surface intersecting said top surface, said inner surface forming a cavity for receiving a die; selectively etching part of said conductive portion; and applying solder resist to a portion of a top surface of said conductive portion.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: October 10, 2017
    Assignee: ENABLINK TECHNOLOGIES LIMITED
    Inventor: Ka Wa Cheung
  • Publication number: 20170278721
    Abstract: A method and apparatus for fabricating a carrier having a top surface and a bottom surface, the method comprising combining a conductive portion at the top surface and a dielectric at the bottom surface, wherein the dielectric includes contact island cavities, filling one or more of the contact island cavities with solder metal to form solder islands, selectively metal plating the conductive portion, selectively etching a portion of the conductive portion, and applying solder resist to the selectively plated and etched top surface of said conductive portion.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Inventor: Ka Wa CHEUNG
  • Patent number: 9735032
    Abstract: A method of fabricating a BGA carrier, the method comprising combining a conductive portion and a molded dielectric portion, the dielectric portion having a top surface, a bottom surface and an inner surface, the inner surface intersecting said top surface and said bottom surface, the inner surface forming a cavity for receiving a semiconductor die; selectively bonding the semiconductor die to a top surface of the conductive portion; selectively etching part of the conductive portion; and applying solder resist to a bottom surface of the conductive portion.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 15, 2017
    Assignee: ENABLINK TECHNOLOGIES LIMITED
    Inventor: Ka Wa Cheung
  • Patent number: 9711376
    Abstract: A method and apparatus for fabricating a carrier having a top surface and a bottom surface, the method comprising combining a conductive portion at the top surface and a dielectric at the bottom surface, wherein the dielectric includes contact island cavities, filling one or more of the contact island cavities with solder metal to form solder islands, selectively metal plating the conductive portion, selectively etching a portion of the conductive portion, and applying solder resist to the selectively plated and etched top surface of said conductive portion.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: July 18, 2017
    Assignee: ENABLINK TECHNOLOGIES LIMITED
    Inventor: Ka Wa Cheung
  • Publication number: 20150162218
    Abstract: A method of fabricating a receptacle down BGA carrier having a top surface and a bottom surface, the method comprising combining a conductive portion and a molded dielectric portion, said dielectric portion having an inner surface intersecting said top surface, said inner surface forming a cavity for receiving a die; selectively etching part of said conductive portion; and applying solder resist to a portion of a top surface of said conductive portion.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 11, 2015
    Inventor: Ka Wa CHEUNG
  • Publication number: 20150162215
    Abstract: A method and apparatus for fabricating a carrier having a top surface and a bottom surface, the method comprising combining a conductive portion at the top surface and a dielectric at the bottom surface, wherein the dielectric includes contact island cavities, filling one or more of the contact island cavities with solder metal to form solder islands, selectively metal plating the conductive portion, selectively etching a portion of the conductive portion, and applying solder resist to the selectively plated and etched top surface of said conductive portion.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 11, 2015
    Inventor: Ka Wa CHEUNG
  • Publication number: 20150162217
    Abstract: A method of fabricating a BGA carrier, the method comprising combining a conductive portion and a molded dielectric portion, the dielectric portion having a top surface, a bottom surface and an inner surface, the inner surface intersecting said top surface and said bottom surface, the inner surface forming a cavity for receiving a semiconductor die; selectively bonding the semiconductor die to a top surface of the conductive portion; selectively etching part of the conductive portion; and applying solder resist to a bottom surface of the conductive portion.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 11, 2015
    Inventor: Ka Wa CHEUNG