Abstract: Red-emitting phosphors may comprise a nitride-based composition represented by the chemical formula MaSrbSicAldNeEuf, wherein: M is at least one of Mg, Ca, Sr, Ba, Y, Li, Na, K and Zn, and 0<a<1.0; 1.5<b<2.5; 4.0?c?5.0; 0?d?1.0; 7.5<e<8.5; and 0<f<0.1; wherein a+b+f>2+d/v and v is the valence of M. Furthermore, nitride-based red-emitting phosphor compositions may be represented by the chemical formula MxM?2Si5-yAlyN8:A, wherein: M is Mg, Ca, Sr, Ba, Y, Li, Na, K and Zn, and x>0; M? is at least one of Mg, Ca, Sr, Ba, and Zn; 0?y?0.15; and A is at least one of Eu, Ce, Tb, Pr, and Mn; wherein x>y/v and v is the valence of M, and wherein the red-emitting phosphors have the general crystalline structure of M?2Si5N8:A.

Abstract: An apparatus includes a wafer portion and a plurality of die fabricated in the wafer portion in a defined pattern such that the die are separated from each other by a dicing area or a street. The apparatus includes a conductive connection between given adjacent die. The conductive connection is electrically coupled to circuitry disposed on the given adjacent die.

Abstract: Red-emitting phosphors may comprise a nitride-based composition represented by the chemical formula MaSrbSicAldNeEuf, wherein: M is at least one of Mg, Ca, Sr, Ba, Y, Li, Na, K and Zn, and 0<a<1.0; 1.5<b<2.5; 4.0?c?5.0; 0?d?1.0; 7.5<e<8.5; and 0<f<0.1; wherein a+b+f>2+d/v and v is the valence of M. Furthermore, nitride-based red-emitting phosphor compositions may be represented by the chemical formula MxM?2Si5-yAlyN8:A, wherein: M is Mg, Ca, Sr, Ba, Y, Li, Na, K and Zn, and x>0; M? is at least one of Mg, Ca, Sr, Ba, and Zn; 0?y?0.15; and A is at least one of Eu, Ce, Tb, Pr, and Mn; wherein x>y/v and v is the valence of M, and wherein the red-emitting phosphors have the general crystalline structure of M?2Si5N8:A.

Abstract: Red-emitting phosphors may comprise a nitride-based composition represented by the chemical formula MaSrbSicAldNeEuf, wherein: M is at least one of Mg, Ca, Sr, Ba, Y, Li, Na, K and Zn, and 0<a<1.0; 1.5<b<2.5; 4.0?c?5.0; 0?d?1.0; 7.5<e<8.5; and 0<f<0.1; wherein a+b+f>2+d/v and v is the valence of M. Furthermore, nitride-based red-emitting phosphor compositions may be represented by the chemical formula MxM?2Si5-yAlyN8:A, wherein: M is Mg, Ca, Sr, Ba, Y, Li, Na, K and Zn, and x>0; M? is at least one of Mg, Ca, Sr, Ba, and Zn; 0?y?0.15; and A is at least one of Eu, Ce, Tb, Pr, and Mn; wherein x>y/v and v is the valence of M, and wherein the red-emitting phosphors have the general crystalline structure of M?2Si5N8:A.

Abstract: An apparatus includes a wafer portion and a plurality of die fabricated in the wafer portion in a defined pattern such that the die are separated from each other by a dicing area or a street. The apparatus includes a conductive connection between given adjacent die. The conductive connection is electrically coupled to circuitry disposed on the given adjacent die.

Abstract: A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die.

Abstract: Red-emitting phosphors may comprise a nitride-based composition represented by the chemical formula MaSrbSicAldNeEuf, wherein: M is at least one of Mg, Ca, Sr, Ba, Y, Li, Na, K and Zn, and 0<a<1.0; 1.5<b<2.5; 4.0?c?5.0; 0?d?1.0; 7.5<e<8.5; and 0<f<0.1; wherein a+b+f>2+d/v and v is the valence of M. Furthermore, nitride-based red-emitting phosphor compositions may be represented by the chemical formula MxM?2Si5-yAlyN8:A, wherein: M is Mg, Ca, Sr, Ba, Y, Li, Na, K and Zn, and x>0; M? is at least one of Mg, Ca, Sr, Ba, and Zn; 0?y?0.15; and A is at least one of Eu, Ce, Tb, Pr, and Mn; wherein x>y/v and v is the valence of M, and wherein the red-emitting phosphors have the general crystalline structure of M?2Si5N8:A.

Abstract: An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

Abstract: Red-emitting phosphors may comprise a nitride-based composition represented by the chemical formula MaSrbSicAldNeEuf, wherein: M is at least one of Mg, Ca, Sr, Ba, Y, Li, Na, K and Zn, and 0<a<1.0; 1.5<b<2.5; 4.0?c?5.0; 0?d?1.0; 7.5<e<8.5; and 0<f<0.1; wherein a+b+f>2+d/v and v is the valence of M. Furthermore, nitride-based red-emitting phosphor compositions may be represented by the chemical formula MxM?2Si5?yAlyN8:A, wherein: M is Mg, Ca, Sr, Ba, Y, Li, Na, K and Zn, and x>0; M? is at least one of Mg, Ca, Sr, Ba, and Zn; 0?y?0.15; and A is at least one of Eu, Ce, Tb, Pr, and Mn; wherein x>y/v and v is the valence of M, and wherein the red-emitting phosphors have the general crystalline structure of M?2Si5N8:A.

Abstract: An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

Abstract: High voltage isolation capabilities are provided using a first integrated circuit die that includes an inverting circuit path and a non-inverting circuit path coupled to receive a single-ended signal and to generate a differential signal from the single-ended signal for transmission over an isolation link. A second integrated circuit die includes a differential Schmitt trigger circuit coupled to the differential signal communicated over the isolation link and to supply at least one output signal corresponding thereto. An isolation barrier is disposed between the inverting and non-inverting circuit paths and the differential Schmitt trigger circuit and includes at least two isolation capacitors coupled to respectively transmit each portion of the differential signal.

Abstract: An isolator that includes first and second substantially identical circuitry galvanically isolated from each other and each having at least one communications channel thereon for communicating signals across an isolation boundary therebetween and each of said first and second circuitry having configurable functionality associated with the operation thereof. A coupling device is provided for coupling signal across the isolation boundary between the at least one communication channels of the first and second circuitry. First and second configuration memories are provided, each associated with a respective one of the first and second circuitry. First and second configuration control devices are provided, each associated with a respective one of the first and second circuitry and each configuring the functionality of the associated one of the first and second circuitry.

Abstract: High voltage isolation capabilities are provided using a first integrated circuit die that includes an inverting circuit path and a non-inverting circuit path coupled to receive a single-ended signal and to generate a differential signal from the single-ended signal for transmission over an isolation link. A second integrated circuit die includes a differential Schmitt trigger circuit coupled to the differential signal communicated over the isolation link and to supply at least one output signal corresponding thereto. An isolation barrier is disposed between the inverting and non-inverting circuit paths and the differential Schmitt trigger circuit and includes at least two isolation capacitors coupled to respectively transmit each portion of the differential signal.

Abstract: An integrated circuit having voltage isolation capabilities includes a plurality of communications channels for transceiving data from the integrated circuit. Each of the communications channel includes capacitive isolation circuitry located in conductive layers of the integrated circuit for providing a high voltage isolation link. The capacitive isolation circuitry distributes a first portion of a high voltage isolation signal across a first group of capacitors on a first link and a second link in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation signal across a second group of capacitors in the first link and the second link in the capacitive isolation circuitry. A differential receiver on each of the plurality of communications channels receives the data on the first link and the second link.

Abstract: An integrated circuit provides high voltage isolation capabilities. The circuit includes a first area containing a first group of functional circuitry located in a substrate of the integrated circuit. This circuit also includes a second area containing a second group of functional circuitry also contained within the substrate of the integrated circuit. Capacitive isolation circuitry located in the conductive layers in the integrated circuit provide a high voltage isolation link between the first group of functional circuitry and the second group of functional circuitry. The capacitive isolation circuitry distributes a first portion of the high voltage isolation signal across the first group of capacitors in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation circuitry across the second group of capacitors in the capacitive isolation circuitry.

Abstract: A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die.

Abstract: An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry.

Abstract: A digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine.

Abstract: An integrated circuit comprises a first microcontroller unit for executing instructions in accordance with a first clock frequency. The microcontroller located on a first die and includes a first processing core for providing a parallel stream of data in accordance with the first clock frequency. A second microcontroller unit executes instructions in accordance with the first clock frequency. The second microcontroller is located on a second die and includes a second processing core for receiving the parallel stream of data in accordance with the first clock frequency. Capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit provides a high voltage isolation link between the first and the second microcontroller units.

Abstract: An integrated system on a chip includes processing circuitry that performs predefined digital processing functions on the chip. The processing circuitry operates responsive to a regulated voltage. An on-chip boost converter generates the regulated voltage responsive to an off-chip voltage provided by an off chip voltage source. The regulated voltage source has a voltage level greater than the off-chip voltage.