Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a drain region and a source region spaced apart from each other, a semiconductor pattern disposed between the drain region and the source region and comprising a first region and a second region, wherein a thickness of the first region is larger than a thickness of the second region, and the first region is disposed between the drain region and the second region, and a gate electrode intersecting the semiconductor pattern.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.

Abstract: A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.

Abstract: A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.

Abstract: A method for manufacturing a capacitor having a dielectric film formed of a tantalum oxide film. The method includes forming a lower electrode that is electrically connected to an active region of a semiconductor substrate. A pre-treatment film including a component selected from a group consisting of silicon oxide, silicon nitride, and combinations thereof, is formed on the surface of the lower electrode. A dielectric film is formed on the pre-treatment film using a Ta precursor. The dielectric film includes a first dielectric layer deposited at a first temperature selected from a designated temperature range, and a second dielectric layer deposited at a second temperature different from the first temperature and selected from the same designated temperature range. A thermal treatment is thereafter performed on the dielectric film in an oxygen atmosphere.

Abstract: A capacitor fabricating method for a semiconductor device where a dielectric film is thermally treated under hydrogen atmosphere to improve interface characteristics between the dielectric film and an electrode. In the method, a lower electrode is formed on a semiconductor substrate. A dielectric film is formed on the lower electrode. The dielectric film is thermally treated under hydrogen atmosphere. An upper electrode is formed on the dielectric film, thereby completing formation of the capacitor. The thermal treatment under the hydrogen atmosphere is performed at a temperature of 300 to 600.degree. C. using H.sub.2 gas or H.sub.2 plasma for 5 to 60 minutes. Thus, the density of an interface trap between the electrode and the dielectric film of the capacitor is reduced.

Abstract: A method of depositing a thin film for a semiconductor device using a lamp heating type apparatus. In the method, a wafer is loaded into a processing chamber of the apparatus, and the pressure of the chamber and the temperature of a susceptor installed in the chamber are increased to a level higher than a deposition pressure and a deposition temperature, respectively. Then, the pressure of the chamber and the temperature of the susceptor are decreased to the deposition pressure and the deposition temperature, respectively, and a film is deposited on the wafer. The vacuum of the chamber is then released and the gas remaining in the chamber and a source gas injection tube is purged.

Abstract: A method for forming a microelectronic capacitor includes the steps of forming a first conductive layer on a substrate and forming an oxide reducing layer on the first conductive layer opposite the substrate wherein the oxide reducing layer reduces oxidation of the first conductive layer. An oxide layer is formed on the oxide reducing layer opposite the substrate, and a dielectric layer is formed on the oxide layer opposite the substrate wherein the dielectric layer has a dielectric constant that is higher than a dielectric constant of the oxide reducing layer, and higher than a dielectric constant of the oxide layer. In addition, a second conductive layer is formed on the dielectric layer opposite the substrate. Related structures are also discussed.