Abstract: Circuits for adjusting the duty cycle of a clock(s) signal include a negative feedback loop for applying an offset signal to the uncorrected clock signal(s). The offset signal, which corresponds to a duty cycle error of the corrected clock signal(s), adjusts the slicing level of the uncorrected clock signal(s) to cause the duty cycle error to converge toward a predetermined value, for example, zero. The techniques may be used to adjust the duty cycle error of differential clock signals as well as single-ended clock signals.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: Circuits for adjusting the duty cycle of a clock(s) signal include a negative feedback loop for applying an offset signal to the uncorrected clock signal(s). The offset signal, which corresponds to a duty cycle error of the corrected clock signal(s), adjusts the slicing level of the uncorrected clock signal(s) to cause the duty cycle error to converge toward a predetermined value, for example, zero. The techniques may be used to adjust the duty cycle error of differential clock signals as well as single-ended clock signals.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: Techniques relating to aligning data bits in frequency synchronous data channels are disclosed. The techniques include determining a phase relationship between clock signals in a pair of data channels. If the clock signals are determined to be out-of-phase, the data bits in a particular one of the data channels may be reordered.

Abstract: A method and apparatus for detecting the phase difference between an input data signal and a local clock signal is provided. An input data signal is frequency divided and then fed through a series connection of a pair of data latches. Signals provided at the input and outputs of the pair of the data latches are exclusively-ORed to provide a variable width pulse signal and a reference pulse signal that may be used in a phase-locked loop to align the local clock with the input data signal in a predetermined phase relationship. A re-timed data signal is provided by inputting the input data signal to a data latch clocked with an inverted phase-aligned clock signal.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: A digital-to-analog converter for converting binary digital input signals into an analog output signals. The converter has a thermometer decoder for decoding a most significant number of the binary bits of the digital input signal into a number of decoder outputs. Apparatus connected to the thermometer decoder and enabled by the decoder outputs in combination with a least significant number of binary bits of the digital input signal generate an analog output signal corresponding to the binary bit digital input signal.

Abstract: The present invention provides a measurement system and a method of determining characteristics associated with a waveform that compensate for distortion associated therewith. In one embodiment, the measurement system includes a monitoring device that detects distortion in a waveform propagating along the transmission medium. The measurement system further includes a computational subsystem that generates a precompensation signal and precompensation value as a function of the distortion in the waveform. The precompensation value substantially compensates for the distortion when inserted into the waveform as a function of the precompensation signal.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: The present invention provides a distortion precompensator and method of compensating for distortion in a transmission medium and a transmitter employing the same. In one embodiment, the distortion precompensator includes a controller, associated with a transmitter, that employs a predetermined precompensation signal. The distortion precompensator also includes an injector that injects a predetermined precompensation value as a function of the precompensation signal into a waveform propagating along the transmission medium thereby substantially compensating for distortion associated therewith.

Abstract: A method and apparatus for changing the open-loop frequency response of an amplifier in a line driver when the load to the line driver is removed. The load is detected by measuring the current to the load. When the current falls below a predetermined amount, the load is assumed to be disconnected and the open-loop frequency response of the amplifier is changed to shift a dominant pole of the line driver to a sufficiently low frequency to ensure stability of the line driver.

Abstract: A system for aligning the phase of signals generated by a selectable standby clock source which has a predetermined frequency with the phase of signals generated by a selected clock source which has the same frequency as signals generated by the standby clock source. The system comprises (1) a delay line having a plurality of delay elements which is configured to receive the signals generated by the standby clock source so that the output signal of each delay element is a delayed version of the standby clock source; (2) a decoder configured to receive each of the delayed versions of the signals generated by the standby clock signal source and generates a selection signal corresponding to a desired one of the delayed version signals that is aligned with signals generated by the selected clock source within a specifiable phase difference; and (3) a selector configured to receive the selection signal so as to select the desired delayed version signal as a new standby clock source.

Abstract: A frequency synthesizer is supplied with an input signal of frequency .function..sub.i to provide an output signal .function..sub.o where .function..sub.o=.function..sub.i M/N and M and N are integers. The input signal is first applied to a divider circuit for division by M/K where K is an integer and the resultant is applied as inputs to a phase locked loop. The phase locked loop includes a ring oscillator of frequency .function..sub.i N/M, a frequency multiplier circuit for multiplying by K, and a frequency divider circuit for dividing by N. The ring oscillator uses a combinational logic circuit that combines the outputs of four differential delay elements to produce a frequency multiplication of four.

Abstract: A receiver for decoding passband signal pulses transmitted in accordance with a M-ARY phase shift keying modulation scheme, comprises a multiphase sampler for sampling received passband signal pulses in the passband frequency range so as to generate a plurality of digital words corresponding to the sampled passband signal pulses, such that each digital word represents the phase of each sampled passband signal pulse. A phase reference register or other storage device is coupled to the multiphase sampler for storing one of the digital words as a phase reference such that other digital words generated by the multiphase sampler are compared with the digital word corresponding to the phase reference for decoding the passband signal pulses.

Abstract: A rail-to-rail voltage-to-current converter converts a variable differential voltage signal having first and second voltage signal components, to an output current signal. The converter includes a first voltage-to-current converter configured to receive a voltage signal component and a reference voltage signal to provide a substantially linear output current signal. A second voltage-to-current converter receives the other one of the voltage signal components and the reference voltage signal to provide a second substantially linear output current signal. An adder combines the first and second output current signals to provide a substantially linear voltage/current characteristic over a wide range of available voltage signals generated by a power supply.

Abstract: A digital phase detector which generates low jitter when the phase-locked-loop is in lock. A delay line, combined with an UP/DOWN phase detector causes substantial overlap in the UP and DOWN signals from the detector. When the PLL is in lock, the overlapping signals substantially cancel each other out, minimizing the variations in the output frequency. Two approaches are disclosed: one delaying the UP signal sufficiently to overlap the DOWN signal, the other using a delay and an exclusive OR gate to generate the DOWN signal.

Abstract: Briefly, in accordance with one embodiment of the invention, a charge pump comprises: a plurality of transistors coupled in a transistor circuit configuration. The transistor circuit configuration is adapted to be coupled to an electronic circuit. The plurality of transistors are coupled so as to deliver electrical charge to the electronic circuit in response to applied signals as the difference of two substantially predetermined currents.

Abstract: Briefly, in accordance with one embodiment of the invention, a current source comprises: a first and a second current path, the current paths being coupled so as to provide, during circuit operation, first and second currents through the respective current paths in a substantially predetermined direct proportion. The current source further includes an operational amplifier having its respective input terminals coupled to the first and second current paths, the operational amplifier being coupled in a feedback configuration so as to maintain substantially equal voltages between a first and second predetermined point respectively located along the first and second current paths. Furthermore, the respective first and second currents are related to the respective first and second voltages substantially in accordance with the junction diode equation.

Abstract: A line driver having two halves arranged in a push-pull configuration. Each half has a pass transistor, connected between a power supply rail and an output terminal, and an amplifier with an output coupled to the output terminal. Only one of the pass transistors conducts at any given time. A sense transistor, coupled between the power supply rail and the input of the amplifier, varies the output of the amplifier to compensate for variations in the conductivity of the conducting pass transistor. Preferably, the current density in the sense transistor is substantially the same as in the conducting pass transistor.