Patents by Inventor Kadiri R. Reddy

Kadiri R. Reddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4229800
    Abstract: A round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final product of binary digits. The round off logic circuitry is connected in the multiplier for rounding its final product off to a predetermined binary digit without requiring the multiplier to generate any of the less significant binary digits to the right of the predetermined binary digit. Multiplier circuitry otherwise required to generate an unrounded final product prior to round off is eliminated without loss of accuracy in round off.
    Type: Grant
    Filed: December 6, 1978
    Date of Patent: October 21, 1980
    Assignee: American Microsystems, Inc.
    Inventors: Roubik Gregorian, Kadiri R. Reddy