Abstract: A CMOS image sensor and fabricating method thereof enhances a light-receiving capability of an image sensor by preventing poor light-refraction characteristics at the peripheral part of a microlens. The CMOS image sensor includes at least one microlens formed by anistropic etching to have a focusing centerline, a central lens portion, and a peripheral lens portion, wherein the focusing centerline passes through the central lens portion and wherein the peripheral lens portion surrounds the central lens portion. The central lens portion has a first convex curvature based on a first radius and the peripheral lens portion has second convex curvature based on a second radius, wherein the second radius is greater than the first radius.

Abstract: A method of manufacturing a semiconductor device including forming an ONO film on a semiconductor substrate and a hard mask layer on the ONO film, forming a trench by etching the hard mask layer and the ONO film on a field region of the semiconductor substrate using a photo etch process and etching the field region of the semiconductor substrate, and forming a device separator at the trench. The method also includes exposing the ONO film by removing the hard mask layer on the ONO film, and leaving the ONO film only on a prospective SONOS gate in a cell region of the semiconductor substrate and removing the ONO film the remainder region thereof. The method further includes forming a gate oxide film on the semiconductor substrate at an outside of the ONO film, and forming a gate electrode on the gate oxide film and the ONO film, respectively.

Abstract: Disclosed is a method for forming a bonding pad of a semiconductor device. The present invention provides a method for forming a bonding pad of a semiconductor device comprising the steps of: (a) forming a top metal line having a predetermined width on a structure of a semiconductor substrate; (b) forming an insulating layer on the top metal line and the structure of the semiconductor substrate; (c) selectively etching the insulating layer to form a bonding pad which exposes portions of the top metal line; (d) performing a plasma treatment over the semiconductor substrate by using CF4, Ar, and O2 gas.

Abstract: Methods for forming a device isolating barrier, and methods for forming a gate electrode using the device isolation barrier are disclosed. In an illustrated method, a semiconductor device isolating barrier is formed by forming a pad oxide layer and a first nitride layer on a semiconductor substrate; forming a trench region by etching the pad oxide layer and the first nitride layer; forming spacers at sidewalls of the etched pad oxide layer and the etched first nitride layer; forming a first trench by etching the semiconductor substrate using the spacers and the etched first nitride layer as a mask; and, after forming a liner oxide layer and an oxide layer filling the trench, forming the device isolating barrier by flattening the liner oxide layer and the trench oxide layer to expose the etched first nitride layer.

Abstract: Methods for fabricating semiconductor devices are disclosed. An illustrated method includes: etching a semiconductor substrate to form a trench, forming an ONO film on the semiconductor substrate, removing the ONO film from the upper surface of the semiconductor substrate while leaving the ONO film on an inside wall surface of the trench, forming a gate oxide film on the semiconductor substrate adjacent the ONO film, depositing polysilicon on the semiconductor substrate, and selectively removing the polysilicon to form SONOS gate electrodes on the gate oxide film and the trench, respectively. Because opposite sides of the polysilicon gate electrode are covered with an ONO layer, the size of the nitride film may be substantially maximized.

Abstract: Disclosed is a method for forming a bonding pad of a semiconductor device. The present invention provides a method for forming a bonding pad of a semiconductor device comprising the steps of: (a) forming a top metal line having a predetermined width on a structure of a semiconductor substrate; (b) forming an insulating layer on the top metal line and the structure of the semiconductor substrate; (c) selectively etching the insulating layer to form a bonding pad which exposes portions of the top metal line; (d) performing a plasma treatment over the semiconductor substrate by using CF4, Ar, and O2 gas.

Abstract: Methods for forming a device isolating barrier, and methods for forming a gate electrode using the device isolation barrier are disclosed. In an illustrated method, a semiconductor device isolating barrier is formed by forming a pad oxide layer and a first nitride layer on a semiconductor substrate; forming a trench region by etching the pad oxide layer and the first nitride layer; forming spacers at sidewalls of the etched pad oxide layer and the etched first nitride layer; forming a first trench by etching the semiconductor substrate using the spacers and the etched first nitride layer as a mask; and, after forming a liner oxide layer and an oxide layer filling the trench, forming the device isolating barrier by flattening the liner oxide layer and the trench oxide layer to expose the etched first nitride layer.

Abstract: Disclosed are an RF integrated circuit and method for manufacturing the same. The RF integrated circuit comprises an insulating layer including a plurality of windows; epitaxial silicon layers separately formed on the insulating layer; semiconductor elements formed on the epitaxial silicon layers; a PMD layer formed on the epitaxial silicon layers and the insulating layer, and including contacts that connecting the semiconductor elements; a first metal wiring layer formed on the PMD layer; an IMD layer formed on the first metal wiring layer, and including vias connecting the first metal wiring layer; a second metal wiring layer formed on the IMD layer; and a capping layer formed on the second metal wiring layer.

Abstract: Disclosed are an RF integrated circuit and method for manufacturing the same. The RF integrated circuit comprises an insulating layer including a plurality of windows; epitaxial silicon layers separately formed on the insulating layer; semiconductor elements formed on the epitaxial silicon layers; a PMD layer formed on the epitaxial silicon layers and the insulating layer, and including contacts that connecting the semiconductor elements; a first metal wiring layer formed on the PMD layer; an IMD layer formed on the first metal wiring layer, and including vias connecting the first metal wiring layer; a second metal wiring layer formed on the IMD layer; and a capping layer formed on the second metal wiring layer.