Abstract: A memory device is configured to generate a signal having a temperature compensation function. The device includes a mode register configured to store error detection and correction (EDC) mode data, and an EDC pattern generator configured to receive pattern information and period information included in the mode data and to generate an EDC pattern signal based on the pattern information and the period information. The EDC pattern signal is a periodic signal obtained by repeating a signal pattern based on the pattern information at a periodic rate corresponding to a signal period based on the period information. In some cases, the EDC pattern signal may be disabled during a portion of the signal period.

Abstract: A memory device is configured to generate a signal having a temperature compensation function. The device includes a mode register configured to store error detection and correction (EDC) mode data, and an EDC pattern generator configured to receive pattern information and period information included in the mode data and to generate an EDC pattern signal based on the pattern information and the period information. The EDC pattern signal is a periodic signal obtained by repeating a signal pattern based on the pattern information at a periodic rate corresponding to a signal period based on the period information. In some cases, the EDC pattern signal may be disabled during a portion of the signal period.

Abstract: Embodiments of the invention include features in the semiconductor memory device that are configured to receive command signals from a memory controller and selectively output at least a portion of the received command signals back to the memory controller for verification. Embodiments of the invention also provide methods for verifying the proper communication of command signals from a memory controller to a semiconductor memory device. Embodiments of the invention also provide systems and methods for testing memory cells in a semiconductor memory device.

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.

Abstract: Embodiments of the invention include features in the semiconductor memory device that are configured to receive command signals from a memory controller and selectively output at least a portion of the received command signals back to the memory controller for verification. Embodiments of the invention also provide methods for verifying the proper communication of command signals from a memory controller to a semiconductor memory device. Embodiments of the invention also provide systems and methods for testing memory cells in a semiconductor memory device.

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.

Abstract: A voltage level shifter for a semiconductor memory device includes a VPP level control circuit that is configured to detect a VPP voltage and to change the VPP voltage in response to a package burn-in mode signal and a test mode signal independent of at least one direct current voltage generated in response to the package burn-in mode signal.

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.

Abstract: A voltage level shifter for a semiconductor memory device includes a VPP level control circuit that is configured to detect a VPP voltage and to change the VPP voltage in response to a package burn-in mode signal and a test mode signal independent of at least one direct current voltage generated in response to the package burn-in mode signal.

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.