Patents by Inventor Kah Ching Edward Teoh

Kah Ching Edward Teoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for preemptive design verification via partial pattern matching
    Patent number: 8453087
    Abstract: An approach is provided for preemptive design verification via partial pattern matching. Data corresponding to one or more problematic layout patterns associated with an integrated circuit manufacturing process is received. Data corresponding to a block of intellectual property including a layout design is received. At least a boundary of the layout design is scanned against the one or more problematic layout patterns. One or more partial matches of the one or more problematic layout patterns are identified at least at the boundary. Results are generated indicating the one or more partial matches.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: May 28, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Kah Ching Edward Teoh
  • Method and apparatus for pattern adjusted timing via pattern matching
    Patent number: 8453089
    Abstract: An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: May 28, 2013
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Kah Ching Edward Teoh, Vito Dai
  • METHOD AND APPARATUS FOR PATTERN ADJUSTED TIMING VIA PATTERN MATCHING
    Publication number: 20130086542
    Abstract: An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 4, 2013
    Inventors: Kah Ching Edward Teoh, Vito Dai
  • METHOD AND APPARATUS FOR PREEMPTIVE DESIGN VERIFICATION VIA PARTIAL PATTERN MATCHING
    Publication number: 20130031521
    Abstract: An approach is provided for preemptive design verification via partial pattern matching. Data corresponding to one or more problematic layout patterns associated with an integrated circuit manufacturing process is received. Data corresponding to a block of intellectual property including a layout design is received. At least a boundary of the layout design is scanned against the one or more problematic layout patterns. One or more partial matches of the one or more problematic layout patterns are identified at least at the boundary. Results are generated indicating the one or more partial matches.
    Type: Application
    Filed: July 29, 2011
    Publication date: January 31, 2013
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Kah Ching Edward Teoh