Patents by Inventor Kah-Ho Phong

Kah-Ho Phong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7006100
    Abstract: A cache memory system is used in a motion estimation system. The system includes: a first cache memory defined in terms of a first width and a first height, and a second cache memory defined in terms of a second width and a second height, wherein said second height is less than said first height, the cache memory system being operable in one of two modes: the first mode being characterized by banks of memory from the second cache memory being concatenated vertically such that their concatenated height is at least equal to the first height, and said concatenated banks being arranged to be appended to the width of the first cache memory to form a single contiguous address space; and the second mode being characterized by banks of memory from the first and second cache being stacked vertically, and being arranged to be addressed as two separate address spaces.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: February 28, 2006
    Assignee: STMicroelectronics Asia Pacific Pte Ltd.
    Inventors: Kah-Ho Phong, Lucas Y. W. Hui
  • Patent number: 6931066
    Abstract: A method of selecting a motion vector for use in a motion estimation system in which the motion vector defines movement of a block of pixels between a search window and a reference frame.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: August 16, 2005
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Swee-San Tee, Kah-Ho Phong, Jean-Michel Bard, Lucas Y. W. Hui
  • Publication number: 20040179604
    Abstract: A method of selecting a motion vector for use in a motion estimation system in which the motion vector defines movement of a block of pixels between a search window and a reference frame.
    Type: Application
    Filed: November 18, 2003
    Publication date: September 16, 2004
    Applicant: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Swee-San Tee, Kah-Ho Phong, Jean-Michel Bard, Lucas Y. W. Hui
  • Publication number: 20040141554
    Abstract: A cache memory system for use in a motion estimation system is disclosed. The system includes: a first cache memory defined in terms of a first width and a first height, and a second cache memory defined in terms of a second width and a second height, wherein said second height is less than said first height, the cache memory system being operable in one of two modes: the first mode being characterized by banks of memory from the second cache memory being concatenated vertically such that their concatenated height is at least equal to the first height, and said concatenated banks being arranged to be appended to the width of the first cache memory to form a single contiguous address space; and the second mode being characterized by banks of memory from the first and second cache being stacked vertically, and being arranged to be addressed as two separate address spaces.
    Type: Application
    Filed: October 2, 2003
    Publication date: July 22, 2004
    Applicant: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Kah-Ho Phong, Lucas Y.W. Hui