Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.

Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.

Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.

Abstract: Methods, apparatuses, and systems for handling transactions received after a configuration request, the method, for example, comprising: receiving a configuration change request by a transaction-handling logic block; performing a configuration change by the transaction-handling logic block in response to the configuration change request, wherein the logic block is to handle transactions received prior to receipt of the configuration change request differently than transactions received after receipt of the configuration change request; receiving, by the transaction-handling logic block, a first transaction before receiving the configuration change request; receiving, by the transaction-handling logic block, a second transaction after receiving the configuration change request and before the configuration change is complete; differentiating the first transaction from the second transaction based on the order in which the first and second transactions were received relative to receipt of the configuration chang

Abstract: In accordance with embodiments disclosed herein are mechanisms for enabling multiple bus master engines to share the same request channel to a pipelined backbone including: receiving a plurality of unarbitrated grant requests at an agent bus interface from a plurality of masters, each requesting access to a backbone connected via a common request channel; determining which of the unarbitrated grant requests is to issue first as a final grant request; storing a master identifier code for the final grant request into a FIFO buffer, the master identifier code associating the final grant request with the issuing master among the plurality of masters; waiting for a backbone grant; and presenting the master identifier code for the final grant request to an agent bus interface, wherein the agent bus interface communicates a command and data for processing via a backbone responsive to the backbone grant to fulfill the final grant request.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for enabling an agent interfacing with a pipelined backbone to locally handle transactions while obeying an ordering rule including, for example, receiving a transaction which requests access to a backbone; decoding routing destination information from the transaction received, in which the decoded routing destination information designates the transaction to be processed either locally or processed via the backbone; storing the decoded routing destination information and the transaction into a First-In-First-Out (FIFO) buffer; retrieving the decoded routing destination information and the transaction from the FIFO buffer; and processing the transaction locally or via the backbone based on the decoded routing destination information retrieved from the FIFO buffer with the transaction.

Abstract: In accordance with embodiments disclosed herein are mechanisms for enabling multiple bus master engines to share the same request channel to a pipelined backbone including: receiving a plurality of unarbitrated grant requests at an agent bus interface from a plurality of masters, each requesting access to a backbone connected via a common request channel; determining which of the unarbitrated grant requests is to issue first as a final grant request; storing a master identifier code for the final grant request into a FIFO buffer, the master identifier code associating the final grant request with the issuing master among the plurality of masters; waiting for a backbone grant; and presenting the master identifier code for the final grant request to an agent bus interface, wherein the agent bus interface communicates a command and data for processing via a backbone responsive to the backbone grant to fulfill the final grant request.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for enabling an agent interfacing with a pipelined backbone to locally handle transactions while obeying an ordering rule including, for example, receiving a transaction which requests access to a backbone; decoding routing destination information from the transaction received, in which the decoded routing destination information designates the transaction to be processed either locally or processed via the backbone; storing the decoded routing destination information and the transaction into a First-In-First-Out (FIFO) buffer; retrieving the decoded routing destination information and the transaction from the FIFO buffer; and processing the transaction locally or via the backbone based on the decoded routing destination information retrieved from the FIFO buffer with the transaction.

Abstract: Methods, apparatuses, and systems for handling transactions received after a configuration request, the method, for example, comprising: receiving a configuration change request by a transaction-handling logic block; performing a configuration change by the transaction-handling logic block in response to the configuration change request, wherein the logic block is to handle transactions received prior to receipt of the configuration change request differently than transactions received after receipt of the configuration change request; receiving, by the transaction-handling logic block, a first transaction before receiving the configuration change request; receiving, by the transaction-handling logic block, a second transaction after receiving the configuration change request and before the configuration change is complete; differentiating the first transaction from the second transaction based on the order in which the first and second transactions were received relative to receipt of the configuration chang

Abstract: Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.

Abstract: Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.

Abstract: An embodiment of the present invention is a technique to provide a secure authentication of chipset configuration. A first chipset configuration (CC) register set in an input/output (I/O) manageability engine (ME) partition authenticates and controls enabling a CC functionality. The I/O ME partition manages I/O resources shared with a processor in a secure manner. A second CC register set in a processor interface space provides the CC functionality. The second CC register set includes a global enable register having an enable field securely accessible to the I/O ME partition in a read and write-once accessibility and accessible to the processor via the processor interface space in a read-only accessibility.