Patents by Inventor Kahn C. Evans

Kahn C. Evans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for identification of proper probe placement on printed circuit board
    Patent number: 11181549
    Abstract: A method of probing printed circuit boards that includes providing a circuit board design including a plurality of probe points, and selecting a probe point including a location ink from the plurality of probe points in the circuit board design to be probed on a physical printed circuit board design. The method continues with probing at least one probe point of the plurality of probe points with a probe that activates the location ink. Activation of the location ink by the probe indicates the selected probe point including the locating ink.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jason T. Albert, Matthew S. Doyle, Christopher J. Engel, Kahn C. Evans, Steven B. Janssen, Matt K. Light
  • IMPLEMENTING PRIORITIZED ORDER SCORING
    Publication number: 20200134542
    Abstract: A method, system and computer program product are provided for implementing enhanced prioritized order scoring based upon user location and user history. A prioritized order score used for work prioritization is calculated using user location and user history. A respective prioritized order score is identified for an ordered pickup location and an alternative pickup location. The identified prioritized order scores are compared to identify a location for the order.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: Jason T. Albert, Matt K. Light, Matthew J. Scheckel, Kahn C. Evans, Steven B. Janssen
  • METHOD FOR IDENTIFICATION OF PROPER PROBE PLACEMENT ON PRINTED CIRCUIT BOARD
    Publication number: 20190285665
    Abstract: A method of probing printed circuit boards that includes providing a circuit board design including a plurality of probe points, and selecting a probe point including a location ink from the plurality of probe points in the circuit board design to be probed on a physical printed circuit board design. The method continues with probing at least one probe point of the plurality of probe points with a probe that activates the location ink. Activation of the location ink by the probe indicates the selected probe point including the locating ink.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Inventors: Jason T. Albert, Matthew S. Doyle, Christopher J. Engel, Kahn C. Evans, Steven B. Janssen, Matt K. Light
  • Method for identification of proper probe placement on printed circuit board
    Patent number: 10371718
    Abstract: A method of probing printed circuit boards that includes providing a circuit board design including a plurality of probe points, and selecting a probe point including a location ink from the plurality of probe points in the circuit board design to be probed on a physical printed circuit board design. The method continues with probing at least one probe point of the plurality of probe points with a probe that activates the location ink. Activation of the location ink by the probe indicates the selected probe point including the locating ink.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason T. Albert, Matthew S. Doyle, Christopher J. Engel, Kahn C. Evans, Steven B. Janssen, Matt K. Light
  • METHOD FOR IDENTIFICATION OF PROPER PROBE PLACEMENT ON PRINTED CIRCUIT BOARD
    Publication number: 20180136255
    Abstract: A method of probing printed circuit boards that includes providing a circuit board design including a plurality of probe points, and selecting a probe point including a location ink from the plurality of probe points in the circuit board design to be probed on a physical printed circuit board design. The method continues with probing at least one probe point of the plurality of probe points with a probe that activates the location ink. Activation of the location ink by the probe indicates the selected probe point including the locating ink.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 17, 2018
    Inventors: Jason T. Albert, Matthew S. Doyle, Christopher J. Engel, Kahn C. Evans, Steven B. Janssen, Matt K. Light
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Duplicate post handling with natural language processing
    Publication number: 20170212872
    Abstract: A server prevents duplicate posts within a question and answer forum. The server may compare the user question vector to each of the plurality of corpus question vectors to determine the closest match between the user question vector and the corpus question vectors to obtain an identified question and answer row, and determine if the identified Q and A row has a last answer that has a corresponding confidence to the question of the identified Q and A row that exceeds a confidence threshold. Responsive to a positive determination, the server may determine if the user question is similar to a question in the identified Q and A row, and if so the server may determine that the last answer is similar to any answer in the identified Q and A row that is not the last answer, and in response, block the submission of the user question.
    Type: Application
    Filed: January 22, 2016
    Publication date: July 27, 2017
    Inventors: Jason T. Albert, Christopher J. Engel, Kahn C. Evans, Steven B. Janssen, Matt K. Light, David R. Nickel, Karl M. Solie, Michael L. Trantow
  • DUPLICATE POST HANDLING WITH NATURAL LANGUAGE PROCESSING
    Publication number: 20170212916
    Abstract: A method prevents duplicate posts within a question and answer forum. The method may compare the user question vector to each of the plurality of corpus question vectors to determine the closest match between the user question vector and the corpus question vectors to obtain an identified question and answer row, and determine if the identified Q and A row has a last answer that has a corresponding confidence to the question of the identified Q and A row that exceeds a confidence threshold. Responsive to a positive determination, the method may determine if the user question is similar to a question in the identified Q and A row, and if so the server may determine that the last answer is similar to any answer in the identified Q and A row that is not the last answer, and in response, block the submission of the user question.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 27, 2017
    Inventors: Jason T. Albert, Christopher J. Engel, Kahn C. Evans, Steven B. Janssen, Matt K. Light, David R. Nickel, Karl M. Solie, Michael L. Trantow
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20160011996
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9081501
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 14, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Distributed performance counters
    Patent number: 8595389
    Abstract: A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kristan D. Davis, Kahn C. Evans, Alan Gara, David L. Satterfield
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20110219208
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Application
    Filed: January 10, 2011
    Publication date: September 8, 2011
    Applicant: International Business Machines Corporation
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • DISTRIBUTED PERFORMANCE COUNTERS
    Publication number: 20110172968
    Abstract: A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kristan D. Davis, Kahn C. Evans, Alan Gara, David L. Satterfield