Abstract: Some aspects of this disclosure relate to implementing a thread device that can associate with a thread network. The thread device includes a network processor, a first memory, and a host processor communicatively coupled to the network processor and the first memory. The first memory can be a nonvolatile memory with a first level security protection, and configured to store a first dataset including thread network parameters for the network processor to manage network functions for the thread device associated with the thread network. The network processor can be coupled to a second memory to store a second dataset having a same content as the first dataset. The network processor is configured to manage the network functions based on the second dataset. The second memory can be a volatile memory with a second level security protection that is less than the first level security protection.

Abstract: Some aspects of this disclosure relate to implementing a thread device that can associate with a thread network. The thread device includes a network processor, a first memory, and a host processor communicatively coupled to the network processor and the first memory. The first memory can be a nonvolatile memory with a first level security protection, and configured to store a first dataset including thread network parameters for the network processor to manage network functions for the thread device associated with the thread network. The host processor is configured to perform various operations associated with the first dataset stored in the first memory. The network processor can be communicatively coupled to a second memory to store a second dataset, where the second dataset has a same content as the first dataset. The network processor is configured to manage the network functions based on the second dataset.

Abstract: An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.

Abstract: The present disclosure describes apparatuses and techniques for patching boot code of read-only memory (ROM). In some aspects, execution of boot code from a ROM is initiated to start a boot process of a device. Execution of the boot code from the ROM is then interrupted to enable execution of other boot code, such as corrected boot code or additional boot code, from another memory. Once the other boot code is executed, execution of the boot code from the ROM is resumed to continue booting the computing device. By so doing, the corrected boot code or additional boot code can be executed during the boot process effective to patch the boot code stored in the ROM.

Abstract: An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.

Abstract: Systems, methods, and other embodiments associated with implementing security functions are described. According to one embodiment, a device includes a memory storing (i) a plurality of functions and (ii) a mapping of locations of the plurality of functions in the memory. The device includes a processing unit configured to, in response to a request by a process being executed by the processing unit, determine a location in the memory of a security function of the plurality of functions using the mapping. The processing unit is configured to execute the security function for the process from the memory according to the mapping.

Abstract: Systems, methods, and other embodiments associated with implementing security functions are described. According to one embodiment, a device includes a memory storing (i) a plurality of functions and (ii) a mapping of locations of the plurality of functions in the memory. The device includes a processing unit configured to, in response to a request by a process being executed by the processing unit, determine a location in the memory of a security function of the plurality of functions using the mapping. The processing unit is configured to execute the security function for the process from the memory according to the mapping.

Abstract: Systems, methods, and other embodiments associated with implementing security functions in a read-only memory (ROM) are described. According to one embodiment, an device includes a read-only memory (ROM) that stores (i) a plurality of security functions and (ii) a mapping of locations of the plurality of security functions in the ROM. The device also includes a processing unit configured to, in response to a request by a process being executed by the processing unit, determine a location in the ROM of a security function using the mapping, and execute the security function for the process from the ROM.

Abstract: Systems, methods, and other embodiments associated with a secure software resume from low power mode are described. According to one embodiment, a method includes receiving a request to enter a low power mode. In response to the request, the method includes storing a data section in LPDRM, performing a validation function on the data section to compute a validation value, and constructing a resume package that includes the validation value and a location of the data section in the LPDRM. The resume package is stored in the LPDRM for use in resuming operation after exiting low power mode.

Abstract: In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.

Abstract: In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.

Abstract: An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first list of instructions may result, at least in part, from invocation of a first function call. The first list of instructions may include at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions. The portions may be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry. The second and third lists of instructions may implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls. The concurrent processing may involve, at least in part, complementary algorithms.

Abstract: The present disclosure describes apparatuses and techniques for patching boot code of read-only memory (ROM). In some aspects, execution of boot code from a ROM is initiated to start a boot process of a device. Execution of the boot code from the ROM is then interrupted to enable execution of other boot code, such as corrected boot code or additional boot code, from another memory. Once the other boot code is executed, execution of the boot code from the ROM is resumed to continue booting the computing device. By so doing, the corrected boot code or additional boot code can be executed during the boot process effective to patch the boot code stored in the ROM.

Abstract: A system for generating a computing system specific value comprising, a computing system not comprising any specialized hardware to generate a device specific value, a software product tangibly embodied in a machine-readable medium, comprising instructions operable to cause computing system to perform operations comprising: generating a digital value which is substantially dependent on manufacturing variation among like devices of computing system.

Abstract: Systems, methods, and other embodiments associated with implementing security functions in a read-only memory (ROM) are described. According to one embodiment, an device includes a read-only memory (ROM) that stores (i) a plurality of security functions and (ii) a mapping of locations of the plurality of security functions in the ROM. The device also includes a processing unit configured to, in response to a request by a process being executed by the processing unit, determine a location in the ROM of a security function using the mapping, and execute the security function for the process from the ROM.

Abstract: An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first list of instructions may result, at least in part, from invocation of a first function call. The first list of instructions may include at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions. The portions may be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry. The second and third lists of instructions may implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls. The concurrent processing may involve, at least in part, complementary algorithms.

Abstract: A system for generating a computing system specific value comprising, a computing system not comprising any specialized hardware to generate a device specific value, a software product tangibly embodied in a machine-readable medium, comprising instructions operable to cause computing system to perform operations comprising: generating a digital value which is substantially dependent on manufacturing variation among like devices of computing system.