Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

Abstract: An optical detecting device includes an image capturing device and a processor. The processor is coupled to a light source and an image capturing device. The processor is configured to adjust a light intensity of the light source for irradiating a correction object in order that a gray value of at least one image block, captured by the image capturing device, of the correction object matches a target correction value, and record a target light intensity while the target light intensity matches the target correction value; control the light source to irradiate light on a testing object with the target light intensity, and control the image capturing device to capture a testing object image of the testing object; and calculate ratios of a target gray value to the gray value of a plurality of pixels of the testing object image to obtain a mapping table.

Abstract: A memory structure including a substrate, a charge storage layer, a first gate, a first dielectric layer, and a second dielectric layer is provided. The substrate includes a memory cell region. The charge storage layer is located on the substrate in the memory cell region. The charge storage layer has a recess. The charge storage layer has a tip around the recess. The first gate is located on the charge storage layer. The first dielectric layer is located between the charge storage layer and the substrate. The second dielectric layer is located between the first gate and the charge storage layer.

Abstract: A memory structure including a substrate, a charge storage layer, a first gate, a first dielectric layer, and a second dielectric layer is provided. The substrate includes a memory cell region. The charge storage layer is located on the substrate in the memory cell region. The charge storage layer has a recess. The charge storage layer has a tip around the recess. The first gate is located on the charge storage layer. The first dielectric layer is located between the charge storage layer and the substrate. The second dielectric layer is located between the first gate and the charge storage layer.

Abstract: An image inspection method includes capturing a target object image, which the target object image comprises a plurality of graphical features; choosing a block image comprising a specific graphical feature of the plurality of graphical features from the target object image; capturing all the graphical features of the block image to obtain a region of interest (ROI); executing a filtering process or a recovering process on the ROI to obtain a pre-processed region; and inspecting, according to the pre-processed region, the target object image to determine whether the target object image has defects.

Abstract: An image inspection method includes capturing a target object image, which the target object image comprises a plurality of graphical features; choosing a block image comprising a specific graphical feature of the plurality of graphical features from the target object image; capturing all the graphical features of the block image to obtain a region of interest (ROI); executing a filtering process or a recovering process on the ROI to obtain a pre-processed region; and inspecting, according to the pre-processed region, the target object image to determine whether the target object image has defects.

Abstract: An optical detecting device includes an image capturing device and a processor. The processor is coupled to a light source and an image capturing device. The processor is configured to adjust a light intensity of the light source for irradiating a correction object in order that a gray value of at least one image block, captured by the image capturing device, of the correction object matches a target correction value, and record a target light intensity while the target light intensity matches the target correction value; control the light source to irradiate light on a testing object with the target light intensity, and control the image capturing device to capture a testing object image of the testing object; and calculate ratios of a target gray value to the gray value of a plurality of pixels of the testing object image to obtain a mapping table.

Abstract: A surface pattern detecting method includes: capturing a surface image of a sample element to be detected, wherein the surface image containing N grayscale pixels and wherein the N is a positive integer; selecting f×N pixels with small grayscale value based on a selection ratio f in order to define a pattern zone and further calculating a pattern mean of the pattern zone based on pixel amount and grayscale value of the pattern zone; selecting f×N pixels with big grayscale value in order to define a background zone and further calculating a background mean of the background zone based on pixel amount and grayscale value of the background zone; and determining whether the surface image has a defect based on the pattern means of the pattern zone and the background mean of the background zone.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell and periphery areas. A patterning step is performed to form first and second stacked structures on the substrate respectively in the cell and periphery areas. First and second spacers are formed respectively on sidewalls of the first and second stacked structures. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell and periphery areas. A patterning step is performed to form first and second stacked structures on the substrate respectively in the cell and periphery areas. First and second spacers are formed respectively on sidewalls of the first and second stacked structures. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure.

Abstract: A surface pattern detecting method includes: capturing a surface image of a sample element to be detected, wherein the surface image containing N grayscale pixels and wherein the N is a positive integer; selecting f×N pixels with small grayscale value based on a selection ratio f in order to define a pattern zone and further calculating a pattern mean of the pattern zone based on pixel amount and grayscale value of the pattern zone; selecting f×N pixels with big grayscale value in order to define a background zone and further calculating a background mean of the background zone based on pixel amount and grayscale value of the background zone; and determining whether the surface image has a defect based on the pattern means of the pattern zone and the background mean of the background zone.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: A one time programmable memory having a memory cell formed on a substrate is provided. The memory cell has a transistor and an anti-fuse structure. The anti-fuse structure is consisted of a doping region, and a dielectric layer and a conductive layer is formed in the top edge corner region of an isolation structure. The upper surface of the isolation structure is lower than the surface of the substrate so as to expose the top edge corner region. The conductive layer is formed on the isolation structure and covers the top edge corner region. The dielectric layer is formed on the top edge corner region and between the doping region and the conductive layer. The memory cell stores the digital data depending on whether the dielectric layer breaks down or not.

Abstract: A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A mask layer is formed over the first dielectric layer. The mask layer, the first dielectric layer and the substrate are patterned to form trenches in the substrate. An isolation layer is formed to fill the trenches. The mask layer and part of the isolation layer are removed to expose the surface of the first dielectric layer. The first dielectric layer of the low voltage circuit region is removed to expose the surface of the substrate. A second dielectric layer having a thickness smaller than the first dielectric layer is formed on the substrate in the low voltage circuit region.

Abstract: A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A mask layer is formed over the first dielectric layer. The mask layer, the first dielectric layer and the substrate are patterned to form trenches in the substrate. An isolation layer is formed to fill the trenches. The mask layer and part of the isolation layer are removed to expose the surface of the first dielectric layer. The first dielectric layer of the low voltage circuit region is removed to expose the surface of the substrate. A second dielectric layer having a thickness smaller than the first dielectric layer is formed on the substrate in the low voltage circuit region.