Patents by Inventor Kai An
Kai An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10050419Abstract: A corona polarization (also denoted “poling”) process and associated apparatus polarizes a ferroelectric polymer thin film while monitoring and evaluating a substrate current whose magnitude, slope and noise profile (Barkhausen noise) varies in accordance with phase transformation processes of crystallites within the film and, thereby, provides an indication of the polarization status. The electric current flowing through the microstructures of the thin film can be modeled by an equivalent circuit, within which electrical charges stored in the respective microstructures are denoted by a plurality of discrete components (e.g., capacitors). Alternatively, the process can be modeled in terms of a hysteresis loop of polarization vs. electric field, corresponding to the availability of recombination sites on the thin-film surface.Type: GrantFiled: October 25, 2016Date of Patent: August 14, 2018Assignee: Areesys Technologies, Inc.Inventors: Kai-An Wang, Efrain A. Velazquez, Craig W. Marion, Michael Z. Wong, Albert Ting, Wen-Chieh Geoffrey Lee
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Publication number: 20170310087Abstract: A corona polarization (also denoted “poling”) process and associated apparatus polarizes a ferroelectric polymer thin film while monitoring and evaluating a substrate current whose magnitude, slope and noise profile (Barkhausen noise) varies in accordance with phase transformation processes of crystallites within the film and, thereby, provides an indication of the polarization status. The electric current flowing through the microstructures of the thin film can be modeled by an equivalent circuit, within which electrical charges stored in the respective microstructures are denoted by a plurality of discrete components (e.g., capacitors). Alternatively, the process can be modeled in terms of a hysteresis loop of polarization vs. electric field, corresponding to the availability of recombination sites on the thin-film surface.Type: ApplicationFiled: October 25, 2016Publication date: October 26, 2017Inventors: Kai-An Wang, Efrain A. Velazquez, Craig W. Marion, Michael Z. Wong, Albert Ting, Wen-Chieh Geoffrey Lee
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Patent number: 9303312Abstract: A deposition system includes a magnetron sputter deposition source that includes a backing frame that includes a window and a closed loop around the window. The backing frame includes inside surfaces towards the window, one or more sputtering targets mounted on inside surfaces of the backing frame, and one or more magnets mounted on outside surfaces of the backing frame. The one or more sputtering targets include sputtering surfaces that define internal walls of the window. The one or more magnets can produce a magnetic field near the one or more sputtering surfaces. A substrate includes a deposition surface oriented towards the window in the backing frame. The deposition surface receives sputtering material(s) from the one or more sputtering targets.Type: GrantFiled: February 25, 2014Date of Patent: April 5, 2016Assignee: Areesys Technologies, Inc.Inventors: Kai-An Wang, Craig W. Marion, Efrain A. Velazquez, Michael Z. Wong, Albert Ting, Jingru Sun
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Publication number: 20150232907Abstract: An automated toxicity assessment apparatus includes multiple sample plates each configured to hold test wells for holding a test solution comprising a test compound and a test organism. A dispense head holds dispense tips for dispensing test solutions into the test wells in one sample plate at each time. An electronic detector can capture an image of a test solution in one of test wells on a sample plate to establish a dose-response curve for the test organism. A carousal system rotates a first sample plate to a first position under the dispense head to allow the plurality of dispense tips to dispense solutions into the test wells on the first sample plate. The carousal system rotates the first sample plate to a second position to allow the electronic detector to capture an image of a test solution in the one of test wells on the first sample plate.Type: ApplicationFiled: January 26, 2015Publication date: August 20, 2015Inventors: Xuejun Wang, Xinhua Zong, Michael Z. Wong, Kai-An Wang
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Publication number: 20150211106Abstract: A flash deposition apparatus includes a liquid delivery system configured to produce fine liquid droplets of an organic material, a heater configured to vaporize the fine liquid droplets to produce a vapor material to be directed to a substrate on which the organic material is deposited; and a radiation shield configured to shield the heater from the liquid delivery system.Type: ApplicationFiled: January 5, 2015Publication date: July 30, 2015Inventors: Kai-An Wang, Jingru Sun, Michael Wong
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Patent number: 8980703Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.Type: GrantFiled: October 3, 2014Date of Patent: March 17, 2015Assignee: Maxchip Electronics Corp.Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
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Publication number: 20150024562Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.Type: ApplicationFiled: October 3, 2014Publication date: January 22, 2015Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
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Patent number: 8907395Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.Type: GrantFiled: September 25, 2011Date of Patent: December 9, 2014Assignee: Maxchip Electronics Corp.Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
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Patent number: 8895386Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell and periphery areas. A patterning step is performed to form first and second stacked structures on the substrate respectively in the cell and periphery areas. First and second spacers are formed respectively on sidewalls of the first and second stacked structures. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure.Type: GrantFiled: October 1, 2012Date of Patent: November 25, 2014Assignee: Maxchip Electronics Corp.Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
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Publication number: 20140326182Abstract: A processing system includes a first processing module that includes a first chamber; and a first processing source that can deposit a first material on a web substrate. An isolation module includes an isolation chamber, and one or more segregation walls that define a sequence of compartments in the isolation chamber. The first chamber is connected to a first compartment in the sequence of compartments. Each of the segregation walls includes an opening to allow the web substrate to pass through. A second processing module includes a second chamber in connection with a last compartment in the sequence of compartments in the isolation module, and a second processing source configured to deposit a second material on the web substrate. A transport mechanism moves the web substrate continuously through the first processing module, the isolation module, and the second processing module.Type: ApplicationFiled: April 11, 2014Publication date: November 6, 2014Applicant: Areesys CorporationInventors: Kai-An Wang, Michael Z. Wong
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Patent number: 8851154Abstract: A cooling module includes a casing with a thermal-transmittance wall having an interior surface and an exterior surface, a coolant inlet, a vapor outlet, and a converting component with a plurality of orifices and dividing an interior of the casing into a coolant chamber and a vaporization chamber. A liquid coolant is ejected through the plurality of orifices to form plumes toward the interior surface of the thermal-transmittance wall and exchange heat with the thermal-transmittance wall resulting in coolant vapor. In a cooling system, a vapor conduit then carries the vapor to a condenser, and a coolant conduit returns the condensed coolant to the cooling module. The cooling system is used to cool a lamp device.Type: GrantFiled: July 29, 2011Date of Patent: October 7, 2014Assignee: MicroBase Technology Corp.Inventors: Kai-An Cheng, Chia-Chen Liao, Chun-Hsien Wu, Hsien-Chun Meng, Hsien Meng
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Publication number: 20140251799Abstract: A deposition system includes a magnetron sputter deposition source that includes a backing frame that includes a window and a closed loop around the window. The backing frame includes inside surfaces towards the window, one or more sputtering targets mounted on inside surfaces of the backing frame, and one or more magnets mounted on outside surfaces of the backing frame. The one or more sputtering targets include sputtering surfaces that define internal walls of the window. The one or more magnets can produce a magnetic field near the one or more sputtering surfaces. A substrate includes a deposition surface oriented towards the window in the backing frame. The deposition surface receives sputtering material(s) from the one or more sputtering targets.Type: ApplicationFiled: February 25, 2014Publication date: September 11, 2014Applicant: Areesys Technologies, Inc.Inventors: Kai-An Wang, Craig W. Marion, Efrain A. Velazquez, Michael Z. Wong, Albert Ting, Jingru Sun
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Publication number: 20140024183Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell and periphery areas. A patterning step is performed to form first and second stacked structures on the substrate respectively in the cell and periphery areas. First and second spacers are formed respectively on sidewalls of the first and second stacked structures. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure.Type: ApplicationFiled: October 1, 2012Publication date: January 23, 2014Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
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Publication number: 20140007621Abstract: A method for manufacturing a polysilicon ingot includes: (a) providing molten silicon in a container; (b) maintaining a surface temperature of the molten silicon higher than its melting point while decreasing the temperature of a base portion of the container to a temperature (T1) lower than the melting point at a rate of at least 2.6° C./min; (c) increasing the temperature of the base portion to a temperature (T2) lower than the melting point; (d) maintaining the surface temperature of the molten silicon higher than the melting point while decreasing and then increasing the temperature of the base portion to a temperature lower than the melting point of silicon; and (e) reducing the temperature of the molten silicon to form the polysilicon ingot.Type: ApplicationFiled: March 18, 2013Publication date: January 9, 2014Applicant: MOTECH INDUSTRIES INC.Inventors: Kai-An Ho, Chien-Kang Chou
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Publication number: 20130302520Abstract: A processing system for depositing a plurality of source materials on a substrate, includes a first thermal evaporation source that can evaporate a first source material to produce a first vapor, a second thermal evaporation source that can evaporate a second source material to produce a second vapor, a vapor mixing chamber that allows the first vapor and the second vapor to be mixed to produce a mixed vapor, and conduits that can separately transport the first vapor and the second vapor to the vapor mixing chamber. The mixed vapor can be directed toward a substrate to deposit a mixture of the first source material and the second source material on the substrate. The processing system can also include vapor filters configured to regulate flows of the first vapor and the second vapor, and a mixed vapor filter to regulate flow of the mixed vapor.Type: ApplicationFiled: July 2, 2012Publication date: November 14, 2013Inventors: Kai-An Wang, Michael Wong, Maosheng Ye, Albert Ting, Enhao Lin
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Publication number: 20130287947Abstract: A deposition apparatus includes one or more evaporation sources each of which includes a container comprising an opening and configured to hold a source material, a source heater adjacent to and in thermal communication with the container, wherein the source heater is configured to elevate temperature of the source material to produce a vapor of the source material, and a source enclosure that encloses the container and the source heater. The source enclosure includes a vent configured to direct the vapor of the source material towards a substrate. The deposition apparatus includes also a plurality of substrate heaters in thermal communication with the substrate. The substrate includes a deposition surface configured to receive deposition of the source material by condensing the vapor. The plurality of substrate heaters can heat different portions of the substrate to different temperatures.Type: ApplicationFiled: April 1, 2013Publication date: October 31, 2013Applicant: AREESYS CORPORATIONInventors: Kai-An Wang, Albert Ting, Enhao Lin, Michael Wong
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Publication number: 20130043522Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.Type: ApplicationFiled: September 25, 2011Publication date: February 21, 2013Applicant: MAXCHIP ELECTRONICS CORP.Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
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Publication number: 20120026745Abstract: A lamp device includes a lamp housing, a light emitting component serving as a heat source and a cooling system. The cooling system includes a liquid coolant, a cooling module, a vapor conduit, a coolant conduit, and a condenser. The cooling module includes a casing and a converting component. The casing has a thermal-transmittance wall having an interior surface and an exterior surface, a coolant inlet and a vapor outlet. The converting component divides an interior of the casing into a coolant chamber and a vaporization chamber. The converting component is formed with a plurality of orifices for permitting the liquid coolant in the coolant chamber to be ejected therethrough to form plumes of the liquid coolant that travel toward the interior surface of the thermal-transmittance wall and that exchange heat with the thermal-transmittance wall to result in coolant vapor flowing out of the vaporization chamber via the vapor outlet.Type: ApplicationFiled: July 29, 2011Publication date: February 2, 2012Inventors: Kai-An Cheng, Chia-Chen Liao, Chun-Hsien Wu, Hsien-Chun Meng, Hsien Meng
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Publication number: 20120008364Abstract: A one time programmable memory having a memory cell formed on a substrate is provided. The memory cell has a transistor and an anti-fuse structure. The anti-fuse structure is consisted of a doping region, and a dielectric layer and a conductive layer is formed in the top edge corner region of an isolation structure. The upper surface of the isolation structure is lower than the surface of the substrate so as to expose the top edge corner region. The conductive layer is formed on the isolation structure and covers the top edge corner region. The dielectric layer is formed on the top edge corner region and between the doping region and the conductive layer. The memory cell stores the digital data depending on whether the dielectric layer breaks down or not.Type: ApplicationFiled: November 1, 2010Publication date: January 12, 2012Applicant: MAXCHIP ELECTRONICS CORP.Inventors: Tung-Ming Lai, Teng-Feng Wang, Kai-An Hsueh
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Patent number: D758988Type: GrantFiled: September 9, 2014Date of Patent: June 14, 2016Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Kai An, Jian-Wei Tang