Abstract: A venting device includes a first flap, which is configured to be actuated to swing upward during a rising time, and a second flap, which is disposed opposite to the first flap and configured to be actuated to swing downward during a falling time, a first actuating portion disposed on the first flap, and a second actuating portion disposed on the second flap. The venting device configured to form a vent is disposed within a wearable sound device or to be disposed within the wearable sound device. The vent is formed via applying a first voltage to the first actuating portion and applying a second voltage on the second actuating portion, such that the venting device gradually forms the vent.

Abstract: Apparatus and method for managing data in a hybrid data storage device. In some embodiments, a hybrid data storage device operates in a normal mode in which data transfer commands received from a host device are serviced by a top level controller circuit which directs a first subset of the received data transfer commands to a non-volatile rotatable recording memory and a second subset of the received data transfer commands are directed to a non-volatile solid-state memory. The controller circuit transitions to a performance mode responsive to a detected first parameter so that subsequently received data transfer commands are directed exclusively to the solid-state memory. The controller circuit terminates the performance mode and resumes the normal mode responsive to a detected second parameter.

Abstract: Apparatus and method for managing data in a hybrid data storage device. In some embodiments, a hybrid data storage device operates in a normal mode in which data transfer commands received from a host device are serviced by a top level controller circuit which directs a first subset of the received data transfer commands to a non-volatile rotatable recording memory and a second subset of the received data transfer commands are directed to a non-volatile solid-state memory. The controller circuit transitions to a performance mode responsive to a detected first parameter so that subsequently received data transfer commands are directed exclusively to the solid-state memory. The controller circuit terminates the performance mode and resumes the normal mode responsive to a detected second parameter.